[PATCH v1 02/17] clk: mediatek: add VDOSYS1 clock
From: Guillaume Ranquet <hidden>
Date: 2022-09-19 16:59:57
Also in:
dri-devel, linux-clk, linux-devicetree, linux-mediatek, linux-phy, lkml
Subsystem:
common clk framework, the rest · Maintainers:
Michael Turquette, Stephen Boyd, Linus Torvalds
From: Pablo Sun <redacted> Add the clock gate definition for the DPI1 hardware in VDOSYS1. The parent clock "hdmi_txpll" is already defined in `mt8195.dtsi`. Signed-off-by: Pablo Sun <redacted> Signed-off-by: Guillaume Ranquet <redacted>
diff --git a/drivers/clk/mediatek/clk-mt8195-vdo1.c b/drivers/clk/mediatek/clk-mt8195-vdo1.c
index d54d7726d186..835335b9d87b 100644
--- a/drivers/clk/mediatek/clk-mt8195-vdo1.c
+++ b/drivers/clk/mediatek/clk-mt8195-vdo1.c@@ -34,6 +34,12 @@ static const struct mtk_gate_regs vdo1_3_cg_regs = { .sta_ofs = 0x140, }; +static const struct mtk_gate_regs vdo1_4_cg_regs = { + .set_ofs = 0x400, + .clr_ofs = 0x400, + .sta_ofs = 0x400, +}; + #define GATE_VDO1_0(_id, _name, _parent, _shift) \ GATE_MTK(_id, _name, _parent, &vdo1_0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
@@ -50,6 +56,9 @@ static const struct mtk_gate_regs vdo1_3_cg_regs = { #define GATE_VDO1_3(_id, _name, _parent, _shift) \ GATE_MTK(_id, _name, _parent, &vdo1_3_cg_regs, _shift, &mtk_clk_gate_ops_setclr) +#define GATE_VDO1_4(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &vdo1_4_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv) + static const struct mtk_gate vdo1_clks[] = { /* VDO1_0 */ GATE_VDO1_0(CLK_VDO1_SMI_LARB2, "vdo1_smi_larb2", "top_vpp", 0),
@@ -107,6 +116,8 @@ static const struct mtk_gate vdo1_clks[] = { GATE_VDO1_2(CLK_VDO1_DISP_MONITOR_DPINTF, "vdo1_disp_monitor_dpintf", "top_vpp", 17), /* VDO1_3 */ GATE_VDO1_3(CLK_VDO1_26M_SLOW, "vdo1_26m_slow", "clk26m", 8), + /* VDO1_4 */ + GATE_VDO1_4(CLK_VDO1_DPI1_HDMI, "vdo1_dpi1_hdmi", "hdmi_txpll", 0), }; static int clk_mt8195_vdo1_probe(struct platform_device *pdev)
--
b4 0.10.0-dev
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