Hi Andy,

On Tue, Jun 14, 2022 at 4:19 AM Andy Shevchenko
[off-list ref] wrote:

On Mon, Jun 13, 2022 at 9:57 PM Brad Larson [off-list ref] wrote:

quoted

Add support for AMD Pensando Elba SoC which explicitly controls
byte-lane enables on writes.  Add priv_write_l() which is

enabling ?

Changed to enabling

...

quoted

+       void (*priv_write_l)(struct sdhci_cdns_priv *priv, u32 val,

priv_writel

Changed to priv_writel

quoted

+                            void __iomem *reg);

And perhaps leave it on one line.

I also would swap parameters, so address goes first followed by value.

Which is the reverse of writel() parameter ordering which is value,
address.  Should I do this?

...

quoted

+static inline void sdhci_cdns_priv_writel(struct sdhci_cdns_priv *priv,
+                                         u32 val, void __iomem *reg)
+{

quoted

+       if (unlikely(priv->priv_write_l))

First of all, why if (unlikely())-else instead of if (likely())-else?

quoted

+               priv->priv_write_l(priv, val, reg);
+       else
+               writel(val, reg);
+}

It was existing code and never looked at it.  This construct looks to
be widely used however this goes away with the two patch approach
below.

$ find . -name \*.c | xargs grep if | grep unlikely | wc
  18640

Instead of branching each time you do I/O, make sure that callback is
always set and call it unconditionally. In this case you don't need to
have this callback, but maybe just a wrapper on `writel()`. As a
result you may split this to two patches in the first of which you
simply introduce a callback and a writel() wrapper which is assigned
unconditionally to all current chips. In the next you add a new chip
support.

Next version will separate into two patches as described

...

quoted

+       u32 m = (reg & 0x3);
+       u32 msk = (0x3 << (m));
+
+       spin_lock_irqsave(&priv->wrlock, flags);
+       writel(msk << 3, priv->ctl_addr);
+       writew(val, host->ioaddr + reg);
+       spin_unlock_irqrestore(&priv->wrlock, flags);

Too many 3:s as magic. Is it GENMASK() or something else? Perhaps it
needs a definition.

Definitely, changed this to be understandable by inspection.
GENMASK() for word and BIT() for byte makes this more clear.  The 3's
came from bits [6:3] are the byte-lane enables in the control reg
where the lower two bits of the address specify the byte(s) to enable.

/*  Elba control reg bits [6:3] are byte-lane enables */
#define ELBA_BYTE_ENABLE_MASK(x)        ((x) << 3)

elba_priv_write_l(...):
        writel(ELBA_BYTE_ENABLE_MASK(0xf), priv->ctl_addr);
        writel(val, reg);

elba_write_w(...):
        byte_enables = GENMASK(1, 0) << (reg & 0x3);
        writel(ELBA_BYTE_ENABLE_MASK(byte_enables), priv->ctl_addr);
        writew(val, host->ioaddr + reg);

...

quoted

+       u32 m = (reg & 0x3);
+       u32 msk = (0x1 << (m));
+
+       spin_lock_irqsave(&priv->wrlock, flags);
+       writel(msk << 3, priv->ctl_addr);
+       writeb(val, host->ioaddr + reg);
+       spin_unlock_irqrestore(&priv->wrlock, flags);

Ditto.

elba_write_b(...):
        byte_enables = BIT(0) << (reg & 0x3);
        writel(ELBA_BYTE_ENABLE_MASK(byte_enables), priv->ctl_addr);
        writeb(val, host->ioaddr + reg);

...

quoted

+       writel(0x78, priv->ctl_addr);

Magic.

writel(ELBA_BYTE_ENABLE_MASK(0xf), priv->ctl_addr);

...

quoted

+static const struct sdhci_cdns_drv_data sdhci_cdns_drv_data = {
+       .pltfm_data = {
+               .ops = &sdhci_cdns_ops,
+       },
+};
+
+

One blank line is enough.

Removed extra blank line

...

quoted

+       {
+               .compatible = "amd,pensando-elba-sd4hc",
+               .data = &sdhci_elba_drv_data

Leave a comma here.

Added comma

Regards,
Brad

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel