RE: [PATCH] arm64: dts: exynos: correct GIC CPU interfaces address range on Exynos7

-----Original Message-----
From: Marc Zyngier <maz@kernel.org>
Sent: 05 August 2021 15:31
To: Alim Akhtar <alim.akhtar@samsung.com>
Cc: 'Krzysztof Kozlowski' <redacted>; 'Rob

Herring'

[off-list ref]; devicetree@vger.kernel.org; linux-arm-
kernel@lists.infradead.org; linux-samsung-soc@vger.kernel.org; linux-
kernel@vger.kernel.org; 'Chanwoo Choi' [off-list ref];
'Pankaj Dubey' [off-list ref]; 'Sam Protsenko'
[off-list ref]
Subject: Re: [PATCH] arm64: dts: exynos: correct GIC CPU interfaces

address

range on Exynos7

On Thu, 05 Aug 2021 10:26:14 +0100,
"Alim Akhtar" [off-list ref] wrote:

quoted

Hi Krzysztof,

quoted

-----Original Message-----
From: Krzysztof Kozlowski <redacted>
Sent: 05 August 2021 13:07
To: Rob Herring <robh+dt@kernel.org>; devicetree@vger.kernel.org;
linux- arm-kernel@lists.infradead.org;
linux-samsung-soc@vger.kernel.org; linux- kernel@vger.kernel.org
Cc: Alim Akhtar <alim.akhtar@samsung.com>; Chanwoo Choi
[off-list ref]; Pankaj Dubey

[off-list ref];

quoted

quoted

Sam Protsenko [off-list ref]; Marc Zyngier
[off-list ref]
Subject: Re: [PATCH] arm64: dts: exynos: correct GIC CPU interfaces
address range on Exynos7

On 05/08/2021 09:21, Krzysztof Kozlowski wrote:

quoted

The GIC-400 CPU interfaces address range is defined as
0x2000-0x3FFF (by ARM).

Looking at DDI0471B_gic400_r0p1_trm.pdf, CPU interface range is
0x0000 ~ 0x10000

I don't where you are getting this range from. The only 64kB range I'm

aware

of is the optional integration trick to cope with 64kB pages that was
documented in the initial SBSA spec. The HW itself only decodes 8kB for

the

CPU interface.

There was a typo in above range, thanks for the clarification. Got it.

	M.

--
Without deviation from the norm, progress is not possible.

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