RE: [PATCH] arm64: dts: exynos: correct GIC CPU interfaces address range on Exynos7

Hi Krzysztof,

-----Original Message-----
From: Krzysztof Kozlowski <redacted>
Sent: 05 August 2021 13:07
To: Rob Herring <robh+dt@kernel.org>; devicetree@vger.kernel.org; linux-
arm-kernel@lists.infradead.org; linux-samsung-soc@vger.kernel.org; linux-
kernel@vger.kernel.org
Cc: Alim Akhtar <alim.akhtar@samsung.com>; Chanwoo Choi
[off-list ref]; Pankaj Dubey [off-list ref];
Sam Protsenko [off-list ref]; Marc Zyngier
[off-list ref]
Subject: Re: [PATCH] arm64: dts: exynos: correct GIC CPU interfaces address
range on Exynos7

On 05/08/2021 09:21, Krzysztof Kozlowski wrote:

quoted

The GIC-400 CPU interfaces address range is defined as 0x2000-0x3FFF
(by ARM).

Looking at DDI0471B_gic400_r0p1_trm.pdf, CPU interface range is 0x0000 ~ 0x10000

I underestimated the issue - this is actually bug as there is a GICC_DIR
register at offset 0x1000. Therefore:

Looking at the exynos7 and exynos5433 UMs looks like GICC_DIR is at offset 0x2100 (from 0x1100_0000 GIC base)
It is possible for you to cross check once?

Fixes: b9024cbc937d ("arm64: dts: Add initial device tree support for
exynos7")

quoted

Reported-by: Sam Protsenko <semen.protsenko@linaro.org>
Reported-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Krzysztof Kozlowski <redacted>
---
 arch/arm64/boot/dts/exynos/exynos7.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi

b/arch/arm64/boot/dts/exynos/exynos7.dtsi
index 8b06397ba6e7..c73a597ca66e 100644

--- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi

@@ -137,7 +137,7 @@ gic: interrupt-controller@11001000 {
 			#address-cells = <0>;
 			interrupt-controller;
 			reg =	<0x11001000 0x1000>,
-				<0x11002000 0x1000>,
+				<0x11002000 0x2000>,
 				<0x11004000 0x2000>,
 				<0x11006000 0x2000>;
 		};

Best regards,
Krzysztof

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