Thread (34 messages) flat view 34 messages, 7 authors, 2021-07-23

Re: [PATCH v4 04/11] perf/x86: Add barrier after updating bts

From: Peter Zijlstra <peterz@infradead.org>
Date: 2021-07-13 13:02:23
Also in: linux-perf-users, lkml

On Sun, Jul 11, 2021 at 06:40:58PM +0800, Leo Yan wrote:
quoted hunk ↗ jump to hunk
Add barrier wmb() to separate the AUX data store and aux_head store.

Signed-off-by: Leo Yan <redacted>
---
 arch/x86/events/intel/bts.c | 3 +++
 1 file changed, 3 insertions(+)
diff --git a/arch/x86/events/intel/bts.c b/arch/x86/events/intel/bts.c
index 6320d2cfd9d3..4a015d160bc5 100644
--- a/arch/x86/events/intel/bts.c
+++ b/arch/x86/events/intel/bts.c
@@ -209,6 +209,9 @@ static void bts_update(struct bts_ctx *bts)
 	} else {
 		local_set(&buf->data_size, head);
 	}
+
+	/* The WMB separates data store and aux_head store matches. */
+	wmb();
Alexander, last time you mentioned (on IRC) that BTS is supposed to be
coherent, in which case we can probably get away with just a compiler
barrier. Can you confirm?

That said; this BTS crud is so horrifically slow, an extra MFENCE isn't
going to matter one way or another.

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
Keyboard shortcuts
hback out one level
jnext message in thread
kprevious message in thread
ldrill in
Escclose help / fold thread tree
?toggle this help