Re: [PATCH 0/3] arm64: Fix cpuidle with pseudo-NMI enabled

On Fri, Jun 11, 2021 at 09:19:22AM +0100, Marc Zyngier wrote:

Hi Lorenzo,

On Thu, 10 Jun 2021 17:28:23 +0100,
Lorenzo Pieralisi [off-list ref] wrote:

quoted

On Tue, Jun 08, 2021 at 06:27:12PM +0100, Marc Zyngier wrote:

quoted

It appears that although cpu_do_idle() is correctly dealing with the
PMR/DAIF duality, the PSCI cpu-suspend code has been left unaware of
it.

On a system that uses PSCI for idle (such as the Ampere Altra I have
access to), the kernel dies as soon as it enters idle (interrupts are
off at the GIC CPU interface level). Boo.

After investigating a bit I realised that this should depend on
ICC_CTLR_EL3.PMHE - if that's clear the PMR should not affect the
GICR->CPU IRQ forwarding (or WakeRequest signal generation when the
GICR_WAKER.ProcessorSleep==1).

You lost me here. I don't see what PMHE has to do here. It is solely
used for 1:N distribution, and is the only way PMR does affect the
propagation of interrupts to the CPU interface. Fortunately, nobody
uses 1:N.

quoted

IIUC if PMHE == 0, the PMR plays no role in wfi completion (and
WakeSignal generation for a CPU/GICR in quiescent state).

Of course it does. PMR gates interrupts *before* they are signalled to
the CPU, meaning that if you keep interrupt masked at the PMR level,
you will never wake up from WFI. Or am I missing your point entirely?

For "simple" wfi (as in executing the wfi instruction) yes. The
IRQs are forwarded to the CPU interface that filters the IRQs based
on priorities and signal the I/F "pin" so that the core wakes up
and wfi completes - forgive me my misunderstanding.

For deep sleep states where GICR_WAKER.ProcessorSleep == 1, the
WakeSignal (ie CPU reset) is generated independently of the PMR
value AFAIK. This means that even *if* an IRQ is supposed to be
masked by the PMR it would wake up a sleeping core _anyway_.

This behaviour is different from shallow C-states (and simple wfi).

That's why I asked what path is causing trouble in
psci_cpu_suspend_enter().

quoted

I assume on Ampere Altra PMHE == 1.

No, it is 0, as indicated by:

<quote>
[    0.000000] GICv3: Pseudo-NMIs enabled using relaxed ICC_PMR_EL1 synchronisation
</quote>

quoted

This changes almost nothing to the need for this patchset but
at least we clarify this behaviour.

Also, we should not be writing ICC_PMR_EL1 when
GICR_WAKER.ProcessorSleep == 1 (which may be set in
gic_cpu_pm_notifier()), this can hang the system.

Why? PMR defines what interrupts will be presented to the CPU
interface and trigger an exception. It doesn't affect putting the CPU
to sleep nor the wake-up.

I don't think we are allowed to have traffic between the CPU IF and
the GICR when ProcessorSleep == 1. So, again IIUC, we can't write
the PMR (if PMHE == 1) after putting the GICR in ProcessorSleep ==1 
because this would sync with the GICR.

quoted

I wonder whether this arm_cpuidle_{save,restore}_context() should
be moved into the gic_cpu_pm_notifier() itself - which would
solve also the PSCI suspend issue Sudeep raised - it would be

Moving from PMR to DAIF masking is something we only do on particular
spots (exception entry/exit, guest entry/exit) as it affects the
behaviour of simple things such as local_irq_*(). Moving it to a
higher level feels super dangerous.

Yes it is dangerous and ugly. It is also true that what needs to
be saved/restore on idle entry is becoming extremely complicated
and hard to track across kernel subsystems and that's unfortunate
too, that's what is causing these bugs.

Thanks,
Lorenzo

quoted

a bit ugly though (CPU PM notifiers are run in S2R and CPUidle
automatically and this would work for any S2R/CPUidle backend
other than PSCI even though that does not/will never exist on
arm64 ;-))

https://lore.kernel.org/linux-arm-kernel/20210608182044.ayqa6fbab4jyz7kp@bogus (local)

I still believe this series is right - just raised these points
for discussion.

Thanks,

	M.

-- 
Without deviation from the norm, progress is not possible.

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