From: Marc Zyngier <maz@kernel.org> Date: 2021-06-08 17:29:04
It appears that although cpu_do_idle() is correctly dealing with the
PMR/DAIF duality, the PSCI cpu-suspend code has been left unaware of
it.
On a system that uses PSCI for idle (such as the Ampere Altra I have
access to), the kernel dies as soon as it enters idle (interrupts are
off at the GIC CPU interface level). Boo.
Instead of spreading more magic code around, I've elected to provide a
pair of helpers (arm_cpuidle_{save,restore}_context()) which do the
heavy lifting.
With that in place, I can finally boot the above system with
irqchip.gicv3_pseudo_nmi=1. I'd welcome feedback from people who may
have experienced similar issues in the past (and on different
machines).
Marc Zyngier (3):
arm64: Add cpuidle context save/restore helpers
arm64: Convert cpu_do_idle() to using cpuidle context helpers
PSCI: Use cpuidle context helpers in psci_cpu_suspend_enter()
arch/arm/include/asm/cpuidle.h | 5 ++++
arch/arm64/include/asm/cpuidle.h | 35 +++++++++++++++++++++++++++
arch/arm64/kernel/process.c | 41 +++++++-------------------------
drivers/firmware/psci/psci.c | 5 ++++
4 files changed, 54 insertions(+), 32 deletions(-)
--
2.30.2
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From: Marc Zyngier <maz@kernel.org> Date: 2021-06-08 17:29:21
As we need to start doing some additional work on all idle
paths, let's introduce a set of macros that will perform
the work related to the GICv3 pseudo-NMI idle entry exit.
Stubs are introduced to 32bit ARM for compatibility.
As these helpers are currently unused, the is no functional
change.
Signed-off-by: Marc Zyngier <maz@kernel.org>
---
arch/arm/include/asm/cpuidle.h | 5 +++++
arch/arm64/include/asm/cpuidle.h | 35 ++++++++++++++++++++++++++++++++
2 files changed, 40 insertions(+)
From: Marc Zyngier <maz@kernel.org> Date: 2021-06-08 17:29:26
Now that we have helpers that are aware of the pseudo-NMI
feature, introduce them to cpu_do_idle(). This allows for
some nice cleanup.
No functional change intended.
Signed-off-by: Marc Zyngier <maz@kernel.org>
---
arch/arm64/kernel/process.c | 41 ++++++++-----------------------------
1 file changed, 9 insertions(+), 32 deletions(-)
From: Marc Zyngier <maz@kernel.org> Date: 2021-06-08 17:29:37
The PSCI CPU suspend code isn't aware of the PMR vs DAIF game,
resulting in a system that locks up if entering CPU suspend
with GICv3 pNMI enabled.
To save the day, teach the suspend code about our new cpuidle
context helpers, which will do everything that's required just
like the usual WFI cpuidle code.
This fixes my Altra system, which would otherwise lock-up at
boot time when booted with irqchip.gicv3_pseudo_nmi=1.
Signed-off-by: Marc Zyngier <maz@kernel.org>
---
drivers/firmware/psci/psci.c | 5 +++++
1 file changed, 5 insertions(+)
@@ -333,13 +333,18 @@ static int psci_suspend_finisher(unsigned long state)intpsci_cpu_suspend_enter(u32state){+structarm_cpuidle_contextcontext;intret;+arm_cpuidle_save_context(&context);+if(!psci_power_state_loses_context(state))ret=psci_ops.cpu_suspend(state,0);elseret=cpu_suspend(state,psci_suspend_finisher);+arm_cpuidle_restore_context(&context);+returnret;}#endif
--
2.30.2
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(I see Lorenzo has replied on the other thread including me where the issue
was reported asking more details)
On Tue, Jun 08, 2021 at 06:27:15PM +0100, Marc Zyngier wrote:
quoted hunk
The PSCI CPU suspend code isn't aware of the PMR vs DAIF game,
resulting in a system that locks up if entering CPU suspend
with GICv3 pNMI enabled.
To save the day, teach the suspend code about our new cpuidle
context helpers, which will do everything that's required just
like the usual WFI cpuidle code.
This fixes my Altra system, which would otherwise lock-up at
boot time when booted with irqchip.gicv3_pseudo_nmi=1.
Signed-off-by: Marc Zyngier <maz@kernel.org>
---
drivers/firmware/psci/psci.c | 5 +++++
1 file changed, 5 insertions(+)
@@ -333,13 +333,18 @@ static int psci_suspend_finisher(unsigned long state)intpsci_cpu_suspend_enter(u32state){+structarm_cpuidle_contextcontext;intret;+arm_cpuidle_save_context(&context);+if(!psci_power_state_loses_context(state))ret=psci_ops.cpu_suspend(state,0);elseret=cpu_suspend(state,psci_suspend_finisher);+arm_cpuidle_restore_context(&context);+
We need similar save/restore for system suspend as well I believe
(psci_system_suspend_enter)
--
Regards,
Sudeep
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It appears that although cpu_do_idle() is correctly dealing with the
PMR/DAIF duality, the PSCI cpu-suspend code has been left unaware of
it.
On a system that uses PSCI for idle (such as the Ampere Altra I have
access to), the kernel dies as soon as it enters idle (interrupts are
off at the GIC CPU interface level). Boo.
Instead of spreading more magic code around, I've elected to provide a
pair of helpers (arm_cpuidle_{save,restore}_context()) which do the
heavy lifting.
With that in place, I can finally boot the above system with
irqchip.gicv3_pseudo_nmi=1. I'd welcome feedback from people who may
have experienced similar issues in the past (and on different
machines).
With pNMIs my Ampere eMAG would always hang at boot, and your patches make
it actually survive. I briefly kicked perf to get some PMU IRQs and that
also seems to be going just fine. Thanks for digging into this mess!
Tested-by: Valentin Schneider <redacted>
Marc Zyngier (3):
arm64: Add cpuidle context save/restore helpers
arm64: Convert cpu_do_idle() to using cpuidle context helpers
PSCI: Use cpuidle context helpers in psci_cpu_suspend_enter()
arch/arm/include/asm/cpuidle.h | 5 ++++
arch/arm64/include/asm/cpuidle.h | 35 +++++++++++++++++++++++++++
arch/arm64/kernel/process.c | 41 +++++++-------------------------
drivers/firmware/psci/psci.c | 5 ++++
4 files changed, 54 insertions(+), 32 deletions(-)
--
2.30.2
It appears that although cpu_do_idle() is correctly dealing with the
PMR/DAIF duality, the PSCI cpu-suspend code has been left unaware of
it.
On a system that uses PSCI for idle (such as the Ampere Altra I have
access to), the kernel dies as soon as it enters idle (interrupts are
off at the GIC CPU interface level). Boo.
Instead of spreading more magic code around, I've elected to provide a
pair of helpers (arm_cpuidle_{save,restore}_context()) which do the
heavy lifting.
With that in place, I can finally boot the above system with
irqchip.gicv3_pseudo_nmi=1. I'd welcome feedback from people who may
have experienced similar issues in the past (and on different
machines).
With pNMIs my Ampere eMAG would always hang at boot, and your patches make
it actually survive. I briefly kicked perf to get some PMU IRQs and that
also seems to be going just fine. Thanks for digging into this mess!
Tested-by: Valentin Schneider <redacted>
Marc Zyngier (3):
arm64: Add cpuidle context save/restore helpers
arm64: Convert cpu_do_idle() to using cpuidle context helpers
PSCI: Use cpuidle context helpers in psci_cpu_suspend_enter()
arch/arm/include/asm/cpuidle.h | 5 ++++
arch/arm64/include/asm/cpuidle.h | 35 +++++++++++++++++++++++++++
arch/arm64/kernel/process.c | 41 +++++++-------------------------
drivers/firmware/psci/psci.c | 5 ++++
4 files changed, 54 insertions(+), 32 deletions(-)
--
2.30.2
From: Lorenzo Pieralisi <hidden> Date: 2021-06-10 16:30:28
On Tue, Jun 08, 2021 at 06:27:12PM +0100, Marc Zyngier wrote:
It appears that although cpu_do_idle() is correctly dealing with the
PMR/DAIF duality, the PSCI cpu-suspend code has been left unaware of
it.
On a system that uses PSCI for idle (such as the Ampere Altra I have
access to), the kernel dies as soon as it enters idle (interrupts are
off at the GIC CPU interface level). Boo.
After investigating a bit I realised that this should depend on
ICC_CTLR_EL3.PMHE - if that's clear the PMR should not affect the
GICR->CPU IRQ forwarding (or WakeRequest signal generation when the
GICR_WAKER.ProcessorSleep==1).
IIUC if PMHE == 0, the PMR plays no role in wfi completion (and
WakeSignal generation for a CPU/GICR in quiescent state).
I assume on Ampere Altra PMHE == 1.
This changes almost nothing to the need for this patchset but
at least we clarify this behaviour.
Also, we should not be writing ICC_PMR_EL1 when
GICR_WAKER.ProcessorSleep == 1 (which may be set in
gic_cpu_pm_notifier()), this can hang the system.
I wonder whether this arm_cpuidle_{save,restore}_context() should
be moved into the gic_cpu_pm_notifier() itself - which would
solve also the PSCI suspend issue Sudeep raised - it would be
a bit ugly though (CPU PM notifiers are run in S2R and CPUidle
automatically and this would work for any S2R/CPUidle backend
other than PSCI even though that does not/will never exist on
arm64 ;-))
https://lore.kernel.org/linux-arm-kernel/20210608182044.ayqa6fbab4jyz7kp@bogus
I still believe this series is right - just raised these points
for discussion.
Thanks,
Lorenzo
Instead of spreading more magic code around, I've elected to provide a
pair of helpers (arm_cpuidle_{save,restore}_context()) which do the
heavy lifting.
With that in place, I can finally boot the above system with
irqchip.gicv3_pseudo_nmi=1. I'd welcome feedback from people who may
have experienced similar issues in the past (and on different
machines).
Marc Zyngier (3):
arm64: Add cpuidle context save/restore helpers
arm64: Convert cpu_do_idle() to using cpuidle context helpers
PSCI: Use cpuidle context helpers in psci_cpu_suspend_enter()
arch/arm/include/asm/cpuidle.h | 5 ++++
arch/arm64/include/asm/cpuidle.h | 35 +++++++++++++++++++++++++++
arch/arm64/kernel/process.c | 41 +++++++-------------------------
drivers/firmware/psci/psci.c | 5 ++++
4 files changed, 54 insertions(+), 32 deletions(-)
--
2.30.2
On Thu, Jun 10, 2021 at 05:28:23PM +0100, Lorenzo Pieralisi wrote:
On Tue, Jun 08, 2021 at 06:27:12PM +0100, Marc Zyngier wrote:
quoted
It appears that although cpu_do_idle() is correctly dealing with the
PMR/DAIF duality, the PSCI cpu-suspend code has been left unaware of
it.
On a system that uses PSCI for idle (such as the Ampere Altra I have
access to), the kernel dies as soon as it enters idle (interrupts are
off at the GIC CPU interface level). Boo.
[...]
I wonder whether this arm_cpuidle_{save,restore}_context() should
be moved into the gic_cpu_pm_notifier() itself - which would
solve also the PSCI suspend issue Sudeep raised - it would be
a bit ugly though (CPU PM notifiers are run in S2R and CPUidle
+1 if possible, I hadn't fully understood the issue to make this
suggestion. But yes if possible, we must to honour the abstraction even
though PSCI is the only user 😄.
automatically and this would work for any S2R/CPUidle backend
other than PSCI even though that does not/will never exist on
arm64 ;-))
I almost wrote the same thing in my earlier email and deleted 😉 before
sending.
--
Regards,
Sudeep
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From: Marc Zyngier <maz@kernel.org> Date: 2021-06-11 08:21:11
Hi Lorenzo,
On Thu, 10 Jun 2021 17:28:23 +0100,
Lorenzo Pieralisi [off-list ref] wrote:
On Tue, Jun 08, 2021 at 06:27:12PM +0100, Marc Zyngier wrote:
quoted
It appears that although cpu_do_idle() is correctly dealing with the
PMR/DAIF duality, the PSCI cpu-suspend code has been left unaware of
it.
On a system that uses PSCI for idle (such as the Ampere Altra I have
access to), the kernel dies as soon as it enters idle (interrupts are
off at the GIC CPU interface level). Boo.
After investigating a bit I realised that this should depend on
ICC_CTLR_EL3.PMHE - if that's clear the PMR should not affect the
GICR->CPU IRQ forwarding (or WakeRequest signal generation when the
GICR_WAKER.ProcessorSleep==1).
You lost me here. I don't see what PMHE has to do here. It is solely
used for 1:N distribution, and is the only way PMR does affect the
propagation of interrupts to the CPU interface. Fortunately, nobody
uses 1:N.
IIUC if PMHE == 0, the PMR plays no role in wfi completion (and
WakeSignal generation for a CPU/GICR in quiescent state).
Of course it does. PMR gates interrupts *before* they are signalled to
the CPU, meaning that if you keep interrupt masked at the PMR level,
you will never wake up from WFI. Or am I missing your point entirely?
I assume on Ampere Altra PMHE == 1.
No, it is 0, as indicated by:
<quote>
[ 0.000000] GICv3: Pseudo-NMIs enabled using relaxed ICC_PMR_EL1 synchronisation
</quote>
This changes almost nothing to the need for this patchset but
at least we clarify this behaviour.
Also, we should not be writing ICC_PMR_EL1 when
GICR_WAKER.ProcessorSleep == 1 (which may be set in
gic_cpu_pm_notifier()), this can hang the system.
Why? PMR defines what interrupts will be presented to the CPU
interface and trigger an exception. It doesn't affect putting the CPU
to sleep nor the wake-up.
I wonder whether this arm_cpuidle_{save,restore}_context() should
be moved into the gic_cpu_pm_notifier() itself - which would
solve also the PSCI suspend issue Sudeep raised - it would be
Moving from PMR to DAIF masking is something we only do on particular
spots (exception entry/exit, guest entry/exit) as it affects the
behaviour of simple things such as local_irq_*(). Moving it to a
higher level feels super dangerous.
a bit ugly though (CPU PM notifiers are run in S2R and CPUidle
automatically and this would work for any S2R/CPUidle backend
other than PSCI even though that does not/will never exist on
arm64 ;-))
https://lore.kernel.org/linux-arm-kernel/20210608182044.ayqa6fbab4jyz7kp@bogus
I still believe this series is right - just raised these points
for discussion.
Thanks,
M.
--
Without deviation from the norm, progress is not possible.
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From: Marc Zyngier <maz@kernel.org> Date: 2021-06-11 08:25:58
Hi Sudeep,
On Thu, 10 Jun 2021 18:43:52 +0100,
Sudeep Holla [off-list ref] wrote:
On Thu, Jun 10, 2021 at 05:28:23PM +0100, Lorenzo Pieralisi wrote:
quoted
On Tue, Jun 08, 2021 at 06:27:12PM +0100, Marc Zyngier wrote:
quoted
It appears that although cpu_do_idle() is correctly dealing with the
PMR/DAIF duality, the PSCI cpu-suspend code has been left unaware of
it.
On a system that uses PSCI for idle (such as the Ampere Altra I have
access to), the kernel dies as soon as it enters idle (interrupts are
off at the GIC CPU interface level). Boo.
[...]
quoted
I wonder whether this arm_cpuidle_{save,restore}_context() should
be moved into the gic_cpu_pm_notifier() itself - which would
solve also the PSCI suspend issue Sudeep raised - it would be
a bit ugly though (CPU PM notifiers are run in S2R and CPUidle
+1 if possible, I hadn't fully understood the issue to make this
suggestion. But yes if possible, we must to honour the abstraction even
though PSCI is the only user 😄.
See my reply to Lorenzo. Once we switch from PMR to DAIF masking, none
of the local interrupt control helpers work anymore. If we start
leaking this change of behaviour at a higher level in the stack, I
have no idea what happens anymore.
Which is why we perform such switching in very localised cases such as
exception, guest entry, and (oh surprise! ;-) cpu_do_idle().
Thanks,
M.
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From: Lorenzo Pieralisi <hidden> Date: 2021-06-11 09:44:00
On Fri, Jun 11, 2021 at 09:19:22AM +0100, Marc Zyngier wrote:
Hi Lorenzo,
On Thu, 10 Jun 2021 17:28:23 +0100,
Lorenzo Pieralisi [off-list ref] wrote:
quoted
On Tue, Jun 08, 2021 at 06:27:12PM +0100, Marc Zyngier wrote:
quoted
It appears that although cpu_do_idle() is correctly dealing with the
PMR/DAIF duality, the PSCI cpu-suspend code has been left unaware of
it.
On a system that uses PSCI for idle (such as the Ampere Altra I have
access to), the kernel dies as soon as it enters idle (interrupts are
off at the GIC CPU interface level). Boo.
After investigating a bit I realised that this should depend on
ICC_CTLR_EL3.PMHE - if that's clear the PMR should not affect the
GICR->CPU IRQ forwarding (or WakeRequest signal generation when the
GICR_WAKER.ProcessorSleep==1).
You lost me here. I don't see what PMHE has to do here. It is solely
used for 1:N distribution, and is the only way PMR does affect the
propagation of interrupts to the CPU interface. Fortunately, nobody
uses 1:N.
quoted
IIUC if PMHE == 0, the PMR plays no role in wfi completion (and
WakeSignal generation for a CPU/GICR in quiescent state).
Of course it does. PMR gates interrupts *before* they are signalled to
the CPU, meaning that if you keep interrupt masked at the PMR level,
you will never wake up from WFI. Or am I missing your point entirely?
For "simple" wfi (as in executing the wfi instruction) yes. The
IRQs are forwarded to the CPU interface that filters the IRQs based
on priorities and signal the I/F "pin" so that the core wakes up
and wfi completes - forgive me my misunderstanding.
For deep sleep states where GICR_WAKER.ProcessorSleep == 1, the
WakeSignal (ie CPU reset) is generated independently of the PMR
value AFAIK. This means that even *if* an IRQ is supposed to be
masked by the PMR it would wake up a sleeping core _anyway_.
This behaviour is different from shallow C-states (and simple wfi).
That's why I asked what path is causing trouble in
psci_cpu_suspend_enter().
quoted
I assume on Ampere Altra PMHE == 1.
No, it is 0, as indicated by:
<quote>
[ 0.000000] GICv3: Pseudo-NMIs enabled using relaxed ICC_PMR_EL1 synchronisation
</quote>
quoted
This changes almost nothing to the need for this patchset but
at least we clarify this behaviour.
Also, we should not be writing ICC_PMR_EL1 when
GICR_WAKER.ProcessorSleep == 1 (which may be set in
gic_cpu_pm_notifier()), this can hang the system.
Why? PMR defines what interrupts will be presented to the CPU
interface and trigger an exception. It doesn't affect putting the CPU
to sleep nor the wake-up.
I don't think we are allowed to have traffic between the CPU IF and
the GICR when ProcessorSleep == 1. So, again IIUC, we can't write
the PMR (if PMHE == 1) after putting the GICR in ProcessorSleep ==1
because this would sync with the GICR.
quoted
I wonder whether this arm_cpuidle_{save,restore}_context() should
be moved into the gic_cpu_pm_notifier() itself - which would
solve also the PSCI suspend issue Sudeep raised - it would be
Moving from PMR to DAIF masking is something we only do on particular
spots (exception entry/exit, guest entry/exit) as it affects the
behaviour of simple things such as local_irq_*(). Moving it to a
higher level feels super dangerous.
Yes it is dangerous and ugly. It is also true that what needs to
be saved/restore on idle entry is becoming extremely complicated
and hard to track across kernel subsystems and that's unfortunate
too, that's what is causing these bugs.
Thanks,
Lorenzo
quoted
a bit ugly though (CPU PM notifiers are run in S2R and CPUidle
automatically and this would work for any S2R/CPUidle backend
other than PSCI even though that does not/will never exist on
arm64 ;-))
https://lore.kernel.org/linux-arm-kernel/20210608182044.ayqa6fbab4jyz7kp@bogus
I still believe this series is right - just raised these points
for discussion.
Thanks,
M.
--
Without deviation from the norm, progress is not possible.
From: Marc Zyngier <maz@kernel.org> Date: 2021-06-11 11:34:11
On Fri, 11 Jun 2021 10:41:34 +0100,
Lorenzo Pieralisi [off-list ref] wrote:
On Fri, Jun 11, 2021 at 09:19:22AM +0100, Marc Zyngier wrote:
quoted
Hi Lorenzo,
On Thu, 10 Jun 2021 17:28:23 +0100,
Lorenzo Pieralisi [off-list ref] wrote:
quoted
On Tue, Jun 08, 2021 at 06:27:12PM +0100, Marc Zyngier wrote:
quoted
It appears that although cpu_do_idle() is correctly dealing with the
PMR/DAIF duality, the PSCI cpu-suspend code has been left unaware of
it.
On a system that uses PSCI for idle (such as the Ampere Altra I have
access to), the kernel dies as soon as it enters idle (interrupts are
off at the GIC CPU interface level). Boo.
After investigating a bit I realised that this should depend on
ICC_CTLR_EL3.PMHE - if that's clear the PMR should not affect the
GICR->CPU IRQ forwarding (or WakeRequest signal generation when the
GICR_WAKER.ProcessorSleep==1).
You lost me here. I don't see what PMHE has to do here. It is solely
used for 1:N distribution, and is the only way PMR does affect the
propagation of interrupts to the CPU interface. Fortunately, nobody
uses 1:N.
quoted
IIUC if PMHE == 0, the PMR plays no role in wfi completion (and
WakeSignal generation for a CPU/GICR in quiescent state).
Of course it does. PMR gates interrupts *before* they are signalled to
the CPU, meaning that if you keep interrupt masked at the PMR level,
you will never wake up from WFI. Or am I missing your point entirely?
For "simple" wfi (as in executing the wfi instruction) yes. The
IRQs are forwarded to the CPU interface that filters the IRQs based
on priorities and signal the I/F "pin" so that the core wakes up
and wfi completes - forgive me my misunderstanding.
No worries. We're talking about the GIC architecture here, which has
the potential to confuse anyone! :D
For deep sleep states where GICR_WAKER.ProcessorSleep == 1, the
WakeSignal (ie CPU reset) is generated independently of the PMR
value AFAIK. This means that even *if* an IRQ is supposed to be
masked by the PMR it would wake up a sleeping core _anyway_.
I'm not sure we can draw this conclusion. It certainly isn't the
behaviour I'm observing. Otherwise, my system would be able to wake-up
without any additional hacks. It may wake-up the CPU interface, but
not the whole core. It is also completely possible that firmware will
use the PMR value as a hint to decide which interrupts can wake up the
CPU if it is so inclined.
This behaviour is different from shallow C-states (and simple wfi).
That's why I asked what path is causing trouble in
psci_cpu_suspend_enter().
It is the one where we don't loose context. Which makes sense, as it
would otherwise behave like a full reset, and we'd end-up with some
sane values.
quoted
quoted
I assume on Ampere Altra PMHE == 1.
No, it is 0, as indicated by:
<quote>
[ 0.000000] GICv3: Pseudo-NMIs enabled using relaxed ICC_PMR_EL1 synchronisation
</quote>
quoted
This changes almost nothing to the need for this patchset but
at least we clarify this behaviour.
Also, we should not be writing ICC_PMR_EL1 when
GICR_WAKER.ProcessorSleep == 1 (which may be set in
gic_cpu_pm_notifier()), this can hang the system.
Why? PMR defines what interrupts will be presented to the CPU
interface and trigger an exception. It doesn't affect putting the CPU
to sleep nor the wake-up.
I don't think we are allowed to have traffic between the CPU IF and
the GICR when ProcessorSleep == 1. So, again IIUC, we can't write
the PMR (if PMHE == 1) after putting the GICR in ProcessorSleep ==1
because this would sync with the GICR.
Hmmm. This restriction isn't obvious to me. There is some vague
threats in 10.1, but nothing concrete. A.4.11 is more explicit, but
doesn't really define what 'traffic' is. It is also tied to the stream
protocol, which isn't actually mandated.
But if it exists, PHME doesn't have any influence on PMR being sent
back to the RD. That can happen at any time (it is just that we
enforce it with a DSB in the case where PHME is set). Note that
do_cpu_idle() already does this, so we'd already be on thin ice. It is
also unclear whether 'traffic' occurs when the group enables are set
to 0, which is the case when we set ProcessorSleep=1.
And to be honest, setting ProcessorSleep=1 in the kernel (which
implies DS=1) has always been pretty odd. I don't know of any HW that
requires it. I'd be tempted to get rid of it for good.
Thanks,
M.
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From: Lorenzo Pieralisi <hidden> Date: 2021-06-11 16:48:27
On Tue, Jun 08, 2021 at 06:27:13PM +0100, Marc Zyngier wrote:
As we need to start doing some additional work on all idle
paths, let's introduce a set of macros that will perform
the work related to the GICv3 pseudo-NMI idle entry exit.
Stubs are introduced to 32bit ARM for compatibility.
As these helpers are currently unused, the is no functional
It looks good to me - maybe I would define it irq_context for clarity
but that's just a naming convention.
Reviewed-by: Lorenzo Pieralisi <redacted>
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From: Lorenzo Pieralisi <hidden> Date: 2021-06-11 16:50:04
On Tue, Jun 08, 2021 at 06:27:14PM +0100, Marc Zyngier wrote:
Now that we have helpers that are aware of the pseudo-NMI
feature, introduce them to cpu_do_idle(). This allows for
some nice cleanup.
No functional change intended.
Signed-off-by: Marc Zyngier <maz@kernel.org>
---
arch/arm64/kernel/process.c | 41 ++++++++-----------------------------
1 file changed, 9 insertions(+), 32 deletions(-)
From: Lorenzo Pieralisi <hidden> Date: 2021-06-11 16:51:40
On Tue, Jun 08, 2021 at 06:27:15PM +0100, Marc Zyngier wrote:
The PSCI CPU suspend code isn't aware of the PMR vs DAIF game,
resulting in a system that locks up if entering CPU suspend
with GICv3 pNMI enabled.
To save the day, teach the suspend code about our new cpuidle
context helpers, which will do everything that's required just
like the usual WFI cpuidle code.
This fixes my Altra system, which would otherwise lock-up at
boot time when booted with irqchip.gicv3_pseudo_nmi=1.
Signed-off-by: Marc Zyngier <maz@kernel.org>
---
drivers/firmware/psci/psci.c | 5 +++++
1 file changed, 5 insertions(+)
We need an additional patch for PSCI suspend, regardless:
Reviewed-by: Lorenzo Pieralisi <redacted>
@@ -333,13 +333,18 @@ static int psci_suspend_finisher(unsigned long state)intpsci_cpu_suspend_enter(u32state){+structarm_cpuidle_contextcontext;intret;+arm_cpuidle_save_context(&context);+if(!psci_power_state_loses_context(state))ret=psci_ops.cpu_suspend(state,0);elseret=cpu_suspend(state,psci_suspend_finisher);+arm_cpuidle_restore_context(&context);+returnret;}#endif
From: Marc Zyngier <maz@kernel.org> Date: 2021-06-12 12:08:06
On Fri, 11 Jun 2021 17:46:57 +0100,
Lorenzo Pieralisi [off-list ref] wrote:
On Tue, Jun 08, 2021 at 06:27:13PM +0100, Marc Zyngier wrote:
quoted
As we need to start doing some additional work on all idle
paths, let's introduce a set of macros that will perform
the work related to the GICv3 pseudo-NMI idle entry exit.
Stubs are introduced to 32bit ARM for compatibility.
As these helpers are currently unused, the is no functional
It looks good to me - maybe I would define it irq_context for clarity
but that's just a naming convention.
would:
struct arm_cpuidle_irq_context { ... };
#define arm_cpuidle_save_irq_context(c) ...
#define arm_cpuidle_restore_irq_context(c) ...
be OK for you?
Reviewed-by: Lorenzo Pieralisi <redacted>
Thanks!
M.
--
Without deviation from the norm, progress is not possible.
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From: Lorenzo Pieralisi <hidden> Date: 2021-06-16 12:09:24
On Sat, Jun 12, 2021 at 01:04:16PM +0100, Marc Zyngier wrote:
On Fri, 11 Jun 2021 17:46:57 +0100,
Lorenzo Pieralisi [off-list ref] wrote:
quoted
On Tue, Jun 08, 2021 at 06:27:13PM +0100, Marc Zyngier wrote:
quoted
As we need to start doing some additional work on all idle
paths, let's introduce a set of macros that will perform
the work related to the GICv3 pseudo-NMI idle entry exit.
Stubs are introduced to 32bit ARM for compatibility.
As these helpers are currently unused, the is no functional