NXP imx8MPlus integrates 2 indentical dwc3 3.30b IP with additional wakeup
logic to support low power, this wakeup logic has a separated interrupt
which can generate events with suspend clock(32K), due to SoC integration
limitation, 64bit address can't be supported for host controller, but the
xhci capability register HCCPARAMS1 AC64 bit is 1, so introduce a new
property snps,xhci-dis-64bit-support-quirk to enable existing quirk
XHCI_NO_64BIT_SUPPORT for OF platforms. 

Li Jun (6):
  dt-bindings: usb: dwc3: add property to disable xhci 64bit support
  usb: host: xhci-plat: add quirk for XHCI_NO_64BIT_SUPPORT
  usb: dwc3: add imx8mp dwc3 glue layer driver
  arm64: dtsi: imx8mp: add usb nodes
  arm64: dts: imx8mp-evk: enable usb1 as host mode
  dt-bindings: usb: dwc3-imx8mp: add imx8mp dwc3 glue bindings

 Documentation/devicetree/bindings/usb/dwc3.txt     |   3 +
 .../devicetree/bindings/usb/fsl,imx8mp-dwc3.yaml   |  87 +++++
 arch/arm64/boot/dts/freescale/imx8mp-evk.dts       |  32 ++
 arch/arm64/boot/dts/freescale/imx8mp.dtsi          |  79 +++++
 drivers/usb/dwc3/Kconfig                           |  10 +
 drivers/usb/dwc3/Makefile                          |   1 +
 drivers/usb/dwc3/dwc3-imx8mp.c                     | 352 +++++++++++++++++++++
 drivers/usb/host/xhci-plat.c                       |   4 +
 8 files changed, 568 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/usb/fsl,imx8mp-dwc3.yaml
 create mode 100644 drivers/usb/dwc3/dwc3-imx8mp.c

-- 
2.7.4


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