Quoting Rajan Vaja (2019-12-04 22:35:58)

zynqmp_clk_divider_round_rate() returns actual divider value
after calculating from parent rate and desired rate, even though
that rate is not supported by single divider of hardware. It is
also possible that such divisor value can be achieved through 2
different dividers. As, Linux tries to set such divisor value(out
of range) in single divider set divider is getting failed.

Fix the same by computing best possible combination of two
divisors which provides more accurate clock rate.

Signed-off-by: Michal Simek <redacted>
Signed-off-by: Tejas Patel <redacted>
Signed-off-by: Rajan Vaja <redacted>
---

Applied to clk-next


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