ZynqMP clock driver can be used for Versal platform also. Add support
for Versal platform in ZynqMP clock driver.

Also this patch series fixes divider calculation, fractional clock
check and adds support for get maximum divider, clock with
CLK_DIVIDER_POWER_OF_TWO flag and warn user if clock users are more
than allowed.

Rajan Vaja (6):
  dt-bindings: clock: Add bindings for versal clock driver
  clk: zynqmp: Extend driver for versal
  clk: zynqmp: Warn user if clock user are more than allowed
  clk: zynqmp: Add support for get max divider
  clk: zynqmp: Fix divider calculation
  clk: zynqmp: Fix fractional clock check

Tejas Patel (1):
  clk: zynqmp: Add support for clock with CLK_DIVIDER_POWER_OF_TWO flag

 .../devicetree/bindings/clock/xlnx,versal-clk.yaml |  67 +++++++++++
 drivers/clk/zynqmp/clk-zynqmp.h                    |   1 +
 drivers/clk/zynqmp/clkc.c                          |   7 +-
 drivers/clk/zynqmp/divider.c                       | 108 ++++++++++++++++--
 drivers/clk/zynqmp/pll.c                           |   9 +-
 drivers/firmware/xilinx/zynqmp.c                   |   2 +
 include/dt-bindings/clock/xlnx-versal-clk.h        | 123 +++++++++++++++++++++
 include/linux/firmware/xlnx-zynqmp.h               |   2 +
 8 files changed, 306 insertions(+), 13 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml
 create mode 100644 include/dt-bindings/clock/xlnx-versal-clk.h

-- 
2.7.4


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