Thread (41 messages) 41 messages, 5 authors, 2018-12-19

Re: [PATCH V3 09/20] clk: tegra: dfll: add CVB tables for Tegra210

From: Stephen Boyd <sboyd@kernel.org>
Date: 2018-12-18 18:42:04
Also in: linux-clk, linux-tegra

Quoting Joseph Lo (2018-12-18 01:12:21)
Add CVB tables with different chip characterization, so that we can
generate the customize OPP table that suitable for different chips with
different SKUs.

The parameter 'tune_high_min_millivolts' is first time introduced in
this patch, which didn't use in the DFLL driver for clock and voltage
tuning before. It will be used later when DFLL in high voltage range.

Signed-off-by: Joseph Lo <redacted>
---
Acked-by: Stephen Boyd <sboyd@kernel.org>


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