Re: [PATCH V3 06/20] clk: tegra: dfll: CVB calculation alignment with the regulator
From: Stephen Boyd <sboyd@kernel.org>
Date: 2018-12-18 18:02:36
Also in:
linux-clk, linux-tegra
Quoting Joseph Lo (2018-12-18 01:12:18)
The CVB table contains calibration data for the CPU DFLL based on process characterization. The regulator step and offset parameters depend on the regulator supplying vdd-cpu, not on the specific Tegra SKU. When using a PWM controlled regulator, the voltage step and offset are determined by the regulator type in use. This is specified in DT. When using an I2C controlled regulator, we can retrieve them from CPU regulator Then pass this information to the CVB table calculation function. Based on the work done of "Peter De Schrijver [off-list ref]" and "Alex Frid [off-list ref]". Signed-off-by: Joseph Lo <redacted> ---
Acked-by: Stephen Boyd <sboyd@kernel.org> _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel