[PATCH V2 09/21] clk: tegra: dfll: add protection for find_vdd_map APIs
From: Joseph Lo <hidden>
Date: 2018-12-13 09:35:13
Also in:
linux-clk, linux-tegra
Subsystem:
common clk framework, tegra clock driver, the rest · Maintainers:
Michael Turquette, Stephen Boyd, Prashant Gaikwad, Linus Torvalds
The DFLL hardware supports both I2C and PWM based regulator. SW driver only touches I2C regulator when generating LUT. And shouldn't touch it anymore once the DFLL is enabled. This patch adds the protection for the APIs that only work with I2C mode to avoid they could be called accidentally. Signed-off-by: Joseph Lo <redacted> --- *V2: - new added patch in V2 --- drivers/clk/tegra/clk-dfll.c | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/drivers/clk/tegra/clk-dfll.c b/drivers/clk/tegra/clk-dfll.c
index b3668073d9b4..93cc86f17f7b 100644
--- a/drivers/clk/tegra/clk-dfll.c
+++ b/drivers/clk/tegra/clk-dfll.c@@ -1534,6 +1534,9 @@ static int find_vdd_map_entry_exact(struct tegra_dfll *td, int uV) { int i, n_voltages, reg_volt_id, align_step; + if (WARN_ON(td->pmu_if == TEGRA_DFLL_PMU_PWM)) + return -EINVAL; + align_step = uV / td->soc->alignment.step_uv; n_voltages = regulator_count_voltages(td->vdd_reg); for (i = 0; i < n_voltages; i++) {
@@ -1558,6 +1561,9 @@ static int find_vdd_map_entry_min(struct tegra_dfll *td, int uV) { int i, n_voltages, reg_volt_id, align_step; + if (WARN_ON(td->pmu_if == TEGRA_DFLL_PMU_PWM)) + return -EINVAL; + align_step = uV / td->soc->alignment.step_uv; n_voltages = regulator_count_voltages(td->vdd_reg); for (i = 0; i < n_voltages; i++) {
--
2.19.2
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