? 2017?6?5? GMT+08:00 ??3:53:50, Marc Zyngier [off-list ref] ??:

On 05/06/17 06:57, Chen-Yu Tsai wrote:

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Hi Marc,

On Mon, May 22, 2017 at 10:25 PM, Chen-Yu Tsai [off-list ref] wrote:

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On Mon, May 22, 2017 at 5:41 PM, Icenowy Zheng [off-list ref]

wrote:

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? 2017?5?22? GMT+08:00 ??5:39:22, Marc Zyngier

[off-list ref] ??:

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On 18/05/17 08:16, Icenowy Zheng wrote:

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Add support for the newly imported compatible for the A64 R_INTC

in

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irq-sunxi-nmi driver.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
Changes in v5:
- Fix A64 R_INTC compatible.

 drivers/irqchip/irq-sunxi-nmi.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/drivers/irqchip/irq-sunxi-nmi.c

b/drivers/irqchip/irq-sunxi-nmi.c

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index 668730c5cb66..5559c1d593bf 100644

--- a/drivers/irqchip/irq-sunxi-nmi.c
+++ b/drivers/irqchip/irq-sunxi-nmi.c

@@ -56,6 +56,12 @@ static struct sunxi_sc_nmi_reg_offs

sun9i_reg_offs

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= {

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     .enable = 0x04,
 };

+static struct sunxi_sc_nmi_reg_offs sun50i_reg_offs = {
+    .ctrl   = 0x0c,
+    .pend   = 0x10,
+    .enable = 0x40,
+};
+

Magic values? Even if no #define is provided, a pointer to the
corresponding documentation would be appreciated (assuming
documentation
exists).

No documents is available for A64 R_INTC.

No code either. In Allwinner's BSP, the interrupts for the PMICs go
through the (closed source) OpenRISC firmware, so there's no driver
for it in the kernel.

The registers line up with the old interrupt controller from the

A10,

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but it seems only the NMI interrupt is wired up.

Is this OK? Or do you want Icenowy to respin a version with defines?

Ideally, I'd like to see some #defines, but given that the rest of the
file is already littered with hard-coded constants, you might as well
do
the whole thing in a subsequent patch that I would merge with these two
patches.

Personally I think the values are self-explained (the variable
name) and used only once in this structure.

Making defines doesn't make the code more clear.

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 static inline void sunxi_sc_nmi_write(struct irq_chip_generic

*gc,

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u32 off,

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                                   u32 val)
 {

@@ -220,3 +226,10 @@ static int __init sun9i_nmi_irq_init(struct

device_node *node,

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     return sunxi_sc_nmi_irq_init(node, &sun9i_reg_offs);
 }
 IRQCHIP_DECLARE(sun9i_nmi, "allwinner,sun9i-a80-nmi",

sun9i_nmi_irq_init);

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+
+static int __init sun50i_nmi_irq_init(struct device_node *node,
+                                 struct device_node *parent)
+{
+    return sunxi_sc_nmi_irq_init(node, &sun50i_reg_offs);
+}
+IRQCHIP_DECLARE(sun50i_nmi, "allwinner,sun50i-a64-r-intc",

sun50i_nmi_irq_init);

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Apart from the above:

Acked-by: Marc Zyngier <redacted>

Let me know how you want this to be merged.

This, and the previous dt bindings patch, can be merged through

whatever

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tree irqchip drivers are merged through. Is that Jason's irqchip

tree?

I'll probably start pushing a branch with all the irqchip patches I've
collected at some point this week, for Thomas to take into 4.13.

Thanks,

M.
-- 
Jazz is not dead. It just smells funny...

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