[PATCH 2/5] clk: sunxi-ng: gate: Support common pre-dividers
From: Maxime Ripard <hidden>
Date: 2017-02-14 09:39:54
Also in:
linux-clk, lkml
On Tue, Feb 14, 2017 at 11:35:23AM +0800, Chen-Yu Tsai wrote:
Some clock gates have a pre-divider between the source input and the gate itself. A notable example is the HSIC 12 MHz clock found on the A83T, which has the 24 MHz main oscillator as its input, and a /2 pre-divider. Signed-off-by: Chen-Yu Tsai <redacted>
Applied, thanks! Maxime -- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 801 bytes Desc: not available URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20170214/1967bfcd/attachment-0001.sig>