[PATCH 04/14] clk: sunxi: add ahb1 clock for A83T

Hello Maxime,


On Tue, Feb 2, 2016 at 9:17 PM, Maxime Ripard
[off-list ref] wrote:

Hi,

On Sun, Jan 31, 2016 at 09:20:56AM +0800, Vishnu Patekar wrote:

quoted

AHB1 on A83T is similar to ahb1 on A31, except parents are different.
clock index 0b1x is PLL6.

Signed-off-by: Vishnu Patekar <redacted>

If the clock is the same but the parents are different, then we don't
need to duplicate all the logic. Simply add the number of parents to
mux_data, and you're all set.

Problem here is: parent 0b10 for A31 ahb1 is AXI, 0b11 is pll6/pre_div.
0b10 and 0b11 is pll6/pre_div.
So, just adding number of parents to mux_data will not solve problem.

Regards,
Vishnu

Maxime

--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com