[PATCH v2 05/10] doc/bindings: Update clk-qoriq bindings for FSL's chassis-3.0 SoCs
From: Bhupesh Sharma <hidden>
Date: 2015-09-04 06:59:12
Also in:
linux-clk
Subsystem:
common clk framework, open firmware and flattened device tree bindings, the rest · Maintainers:
Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Linus Torvalds
This patch updates the 'clk-qoriq' device-tree bindings for chassis-3.0 compliant SoCs from FSL, for e.g. LS2080A Signed-off-by: Bhupesh Sharma <redacted> --- .../devicetree/bindings/clock/qoriq-clock.txt | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
index 16a3ec4..f0a4b1c 100644
--- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
+++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt@@ -14,6 +14,7 @@ Chassis Version Example Chips --------------- ------------- 1.0 p4080, p5020, p5040 2.0 t4240, b4860 +3.0 ls2080a 1. Clock Block Binding
@@ -32,9 +33,11 @@ Required properties: * "fsl,b4420-clockgen" * "fsl,b4860-clockgen" * "fsl,ls1021a-clockgen" - Chassis-version clock strings include: + * "fsl,ls2080a-clockgen" + Chassis clock strings include: * "fsl,qoriq-clockgen-1.0": for chassis 1.0 clocks * "fsl,qoriq-clockgen-2.0": for chassis 2.0 clocks + * "fsl,qoriq-clockgen-3.0": for chassis 3.0 clocks - reg: Describes the address of the device's resources within the address space defined by its parent bus, and resource zero represents the clock register set
@@ -96,18 +99,23 @@ Required properties: - compatible : Should include one of the following: * "fsl,qoriq-core-pll-1.0" for core PLL clocks (v1.0) * "fsl,qoriq-core-pll-2.0" for core PLL clocks (v2.0) + * "fsl,qoriq-core-pll-3.0" for core PLL clocks (v3.0) * "fsl,qoriq-core-mux-1.0" for core mux clocks (v1.0) * "fsl,qoriq-core-mux-2.0" for core mux clocks (v2.0) + * "fsl,qoriq-core-mux-3.0" for core mux clocks (v3.0) * "fsl,qoriq-sysclk-1.0": for input system clock (v1.0). It takes parent's clock-frequency as its clock. * "fsl,qoriq-sysclk-2.0": for input system clock (v2.0). It takes parent's clock-frequency as its clock. + * "fsl,qoriq-sysclk-3.0": for input system clock (v3.0). + It takes parent's clock-frequency as its clock. * "fsl,qoriq-platform-pll-1.0" for the platform PLL clock (v1.0) * "fsl,qoriq-platform-pll-2.0" for the platform PLL clock (v2.0) + * "fsl,qoriq-platform-pll-3.0" for the platform PLL clock (v3.0) - #clock-cells: From common clock binding. The number of cells in a - clock-specifier. Should be <0> for "fsl,qoriq-sysclk-[1,2].0" - clocks, or <1> for "fsl,qoriq-core-pll-[1,2].0" clocks. - For "fsl,qoriq-core-pll-[1,2].0" clocks, the single + clock-specifier. Should be <0> for "fsl,qoriq-sysclk-[1,2,3].0" + clocks, or <1> for "fsl,qoriq-core-pll-[1,2,3].0" clocks. + For "fsl,qoriq-core-pll-[1,2,3].0" clocks, the single clock-specifier cell may take the following values: * 0 - equal to the PLL frequency * 1 - equal to the PLL frequency divided by 2
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1.7.9.5