[PATCH v2 4/9] clk: rockchip: add new clock type and controller for rk3036
From: Stephen Boyd <hidden>
Date: 2015-09-22 22:41:29
Also in:
linux-clk, linux-rockchip, lkml
On 09/17, Xing Zheng wrote:
+ +static void rockchip_rk3036_pll_init(struct clk_hw *hw)
init ops are "discouraged". Could we do this through assigned rates instead?
quoted hunk ↗ jump to hunk
+{ + struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); + const struct rockchip_pll_rate_table *rate; + unsigned int fbdiv, postdiv1, refdiv, postdiv2, dsmpd, frac; + unsigned long drate; + u32 pllcon; + + if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE)) + return;
I don't understand what this one does though. This check isn't in the set rate ops. -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project