[PATCH v3 1/2] mtd: nand: pxa3xx: Fix PIO FIFO draining
From: Maxime Ripard <hidden>
Date: 2015-02-16 16:50:06
Also in:
lkml, stable
On Mon, Feb 16, 2015 at 10:35:50AM -0300, Ezequiel Garcia wrote:
On 02/16/2015 09:51 AM, Maxime Ripard wrote:quoted
The NDDB register holds the data that are needed by the read and write commands. However, during a read PIO access, the datasheet specifies that after each 32 bits read in that register, when BCH is enabled, we have to make sure that the RDDREQ bit is set in the NDSR register.Typo s/32 bits/32 bytes
Good catch, thanks! Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 819 bytes Desc: Digital signature URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20150216/b05f972f/attachment.sig>