[PATCH v3 1/2] mtd: nand: pxa3xx: Fix PIO FIFO draining
From: Boris Brezillon <hidden>
Date: 2015-02-16 13:34:24
Also in:
lkml, stable
Hi Maxime, On Mon, 16 Feb 2015 13:51:11 +0100 Maxime Ripard [off-list ref] wrote:
quoted hunk ↗ jump to hunk
The NDDB register holds the data that are needed by the read and write commands. However, during a read PIO access, the datasheet specifies that after each 32 bits read in that register, when BCH is enabled, we have to make sure that the RDDREQ bit is set in the NDSR register. This fixes an issue that was seen on the Armada 385, and presumably other mvebu SoCs, when a read on a newly erased page would end up in the driver reporting a timeout from the NAND. Cc: <redacted> # v3.14 Signed-off-by: Maxime Ripard <redacted> --- drivers/mtd/nand/pxa3xx_nand.c | 47 ++++++++++++++++++++++++++++++++++++------ 1 file changed, 41 insertions(+), 6 deletions(-)diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c index 96b0b1d27df1..b2d8d6960765 100644 --- a/drivers/mtd/nand/pxa3xx_nand.c +++ b/drivers/mtd/nand/pxa3xx_nand.c@@ -480,6 +480,41 @@ static void disable_int(struct pxa3xx_nand_info *info, uint32_t int_mask) nand_writel(info, NDCR, ndcr | int_mask); } +static void drain_fifo(struct pxa3xx_nand_info *info, void *data, int len) +{ + if (info->ecc_bch) { + int index = 0; + + while (index < (len * 4)) { + u32 timeout; + + __raw_readsl(info->mmio_base + NDDB, data + index, 8); +
Shouldn't you break here if you've read all the data you were expecting ? As I said in my previous review, I don't know what's happening if you wait for RDDREQ when the FIFO has been fully drained.
+ /*
+ * According to the datasheet, when reading
+ * from NDDB with BCH enabled, after each 32
+ * bytes reads, we have to make sure that the
+ * NDSR.RDDREQ bit is set
+ */
+ for (timeout = 0;
+ !(nand_readl(info, NDSR) & NDSR_RDDREQ);
+ timeout++) {
+ if (timeout >= 5) {
+ dev_err(&info->pdev->dev,
+ "Timeout on RDDREQ while draining the FIFO\n");
+ return;
+ }
+
+ mdelay(1);
+ }
+
+ index += 32;
+ }
+ } else {
+ __raw_readsl(info->mmio_base + NDDB, data, len);
+ }
+}Best Regards, Boris -- Boris Brezillon, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com