[PATCH v2 07/18] ARM: dts: DRA7: Change the parent of apll_pcie_in_clk_mux to dpll_pcie_ref_m2ldo_ck
From: Tero Kristo <hidden>
Date: 2014-06-19 11:13:11
Also in:
linux-devicetree, linux-omap, linux-pci, lkml
On 05/29/2014 09:38 AM, Kishon Vijay Abraham I wrote:
From: Keerthy <j-keerthy@ti.com> Change the parent of apll_pcie_in_clk_mux to dpll_pcie_ref_m2ldo_ck from dpll_pcie_ref_ck.
Why? Needs a better changelog also. -Tero
quoted hunk ↗ jump to hunk
Cc: Rajendra Nayak <redacted> Cc: Tero Kristo <redacted> Cc: Paul Walmsley <paul@pwsan.com> Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Kishon Vijay Abraham I <redacted> --- arch/arm/boot/dts/dra7xx-clocks.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi index 55e95c5..44993ec 100644 --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi@@ -1152,7 +1152,7 @@ apll_pcie_in_clk_mux: apll_pcie_in_clk_mux at 4ae06118 { compatible = "ti,mux-clock"; - clocks = <&dpll_pcie_ref_ck>, <&pciesref_acs_clk_ck>; + clocks = <&dpll_pcie_ref_m2ldo_ck>, <&pciesref_acs_clk_ck>; #clock-cells = <0>; reg = <0x021c 0x4>; ti,bit-shift = <7>;