On 03/11, Lorenzo Pieralisi wrote:

On Fri, Mar 07, 2014 at 11:08:56PM +0000, Stephen Boyd wrote:

quoted

Or should we be expressing the L1 cache as well? Something like:

        cpus {  
                #address-cells = <1>;
                #size-cells = <0>;

                cpu at 0 { 
                        compatible = "qcom,krait";
                        device_type = "cpu";
                        reg = <0>;
                        next-level-cache = <&L1_0>;

			L1_0: l1-cache {
				compatible = "arm,arch-cache";
				interrupts = <1 14 0x304>;
				next-level-cache = <&L2>;
			}
                };

                cpu at 1 { 
                        compatible = "qcom,krait";
                        device_type = "cpu";
                        reg = <1>;
                        next-level-cache = <&L1_1>;

			L1_1: l1-cache {
				compatible = "arm,arch-cache";
				interrupts = <1 14 0x304>;
				next-level-cache = <&L2>;
			}
                };

                L2: l2-cache {
                        compatible = "arm,arch-cache";
                        interrupts = <0 2 0x4>;
		};
	};

(I'm also wondering if the 3rd cell of the interrupt binding
should only indicate the CPU that the interrupt property is
inside?)

I am not aware of interrupts associated with vanilla :) "arm,arch-cache"
objects, so I think that should be handled as a "qcom,krait" specific property
(in the cpu node), or you should add another cache binding (compatible) for
that.

As you might have noticed (idle states thread) I am keen on defining objects
for L1 caches explicitly, that patch still requires an ACK though (and
you need to update it since you cannot add an interrupt property for all
"arm,arch-cache" objects. I am sorry for being a pain, but I do not
think that's correct from a HW description standpoint).

Ok. s/arm,arch-cache/qcom,arch-cache/ then. I imagine it is easy
enough to add some bits in the cache binding once it's accepted.

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