Thread (24 messages) 24 messages, 6 authors, 2013-10-30

[PATCH 4/6] edac: Document Krait L1/L2 EDAC driver binding

From: Olof Johansson <hidden>
Date: 2013-10-29 20:22:59
Also in: linux-arm-msm, linux-devicetree, lkml

On Tue, Oct 29, 2013 at 11:00 AM, Stephen Boyd [off-list ref] wrote:
On 10/29/13 01:21, Kumar Gala wrote:
quoted
On Oct 28, 2013, at 7:31 PM, Stephen Boyd wrote:
quoted
The Krait L1/L2 error reporting device is made up of two
interrupts, one per-CPU interrupt for the L1 caches and one
interrupt for the L2 cache.

Cc: <redacted>
Signed-off-by: Stephen Boyd <redacted>
---
.../devicetree/bindings/arm/qcom,krait-cache-erp.txt     | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/qcom,krait-cache-erp.txt
diff --git a/Documentation/devicetree/bindings/arm/qcom,krait-cache-erp.txt b/Documentation/devicetree/bindings/arm/qcom,krait-cache-erp.txt
new file mode 100644
index 0000000..01fe8a8
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/qcom,krait-cache-erp.txt
@@ -0,0 +1,16 @@
+* Qualcomm Krait L1 / L2 cache error reporting
+
+Required properties:
+- compatible: Should be "qcom,krait-cache-erp"
+- interrupts: Should contain the L1/CPU error interrupt number and
+  then the L2 cache error interrupt number
+
+Optional properties:
+- interrupt-names: Should contain the interrupt names "l1_irq" and
+  "l2_irq"
+
+Example:
+    edac {
+            compatible = "qcom,krait-cache-erp";
+            interrupts = <1 9 0xf04>, <0 2 0x4>;
+    };
Why wouldn't we have these as part of cache nodes in the dts?  (which begs the question why we don't have cache nodes?)
In particular, naming the node edac seems like a suboptimal choice,
since that's a very linux-specific name for the error reporting
framework.
I can certainly add cache nodes and cpu nodes and then put the
interrupts in those nodes. I was thinking along those same lines when I
ported this driver but figured it would be good to get something out
there. The only question I have is how am I supposed to hook that up
into the linux device model? Will the edac driver bind to the device
created for the cpus node and the cache node? I guess it will have to be
a driver that binds to two devices.
Or it could bind to one device and look up the info for the other from
the devicetree without relying on the driver core to instantiate
devices.


-Olof
Keyboard shortcuts
hback out one level
jnext message in thread
kprevious message in thread
ldrill in
Escclose help / fold thread tree
?toggle this help