[PATCH 4/6] edac: Document Krait L1/L2 EDAC driver binding
From: Kumar Gala <hidden>
Date: 2013-10-29 08:21:14
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linux-arm-msm, linux-devicetree, lkml
On Oct 28, 2013, at 7:31 PM, Stephen Boyd wrote:
quoted hunk ↗ jump to hunk
The Krait L1/L2 error reporting device is made up of two interrupts, one per-CPU interrupt for the L1 caches and one interrupt for the L2 cache. Cc: <redacted> Signed-off-by: Stephen Boyd <redacted> --- .../devicetree/bindings/arm/qcom,krait-cache-erp.txt | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/qcom,krait-cache-erp.txtdiff --git a/Documentation/devicetree/bindings/arm/qcom,krait-cache-erp.txt b/Documentation/devicetree/bindings/arm/qcom,krait-cache-erp.txt new file mode 100644 index 0000000..01fe8a8 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/qcom,krait-cache-erp.txt@@ -0,0 +1,16 @@ +* Qualcomm Krait L1 / L2 cache error reporting + +Required properties: +- compatible: Should be "qcom,krait-cache-erp" +- interrupts: Should contain the L1/CPU error interrupt number and + then the L2 cache error interrupt number + +Optional properties: +- interrupt-names: Should contain the interrupt names "l1_irq" and + "l2_irq" + +Example: + edac { + compatible = "qcom,krait-cache-erp"; + interrupts = <1 9 0xf04>, <0 2 0x4>; + };
Why wouldn't we have these as part of cache nodes in the dts? (which begs the question why we don't have cache nodes?) - k -- Employee of Qualcomm Innovation Center, Inc. Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation