On 10/06/13 12:15, Michal Simek wrote:

Thankyou for your comments,

Hi,

hmm - that's a nice bug that thunderbird is not able to send this email. :-(
Let's comment it again via gmail.
    diff --git a/arch/arm/boot/dts/stih415.dtsi
    b/arch/arm/boot/dts/stih415.dtsi
    new file mode 100644
    index 0000000..6dcf5b4
    --- /dev/null
    +++ b/arch/arm/boot/dts/stih415.dtsi

...

    +
    +       soc {
    +               #address-cells = <1>;
    +               #size-cells = <1>;
    +               interrupt-parent = <&intc>;
    +               ranges;
    +               compatible      = "simple-bus";



Rob and Grant: what's the purpose of SoC node.
It seems to me odd that SoC is compatible with simple-bus.

All the drivers on this SOC are based on platform bus, so we use
simple-bus, here.

    diff --git a/arch/arm/boot/dts/stih41x.dtsi
    b/arch/arm/boot/dts/stih41x.dtsi
    new file mode 100644
    index 0000000..7321403
    --- /dev/null
    +++ b/arch/arm/boot/dts/stih41x.dtsi
    @@ -0,0 +1,38 @@
    +/ {
    +       #address-cells = <1>;
    +       #size-cells = <1>;
    +
    +       cpus {
    +               #address-cells = <1>;
    +               #size-cells = <0>;
    +               cpu at 0 {
    +                       compatible = "arm,cortex-a9";
    +                       reg = <0>;
    +               };
    +               cpu at 1 {
    +                       compatible = "arm,cortex-a9";
    +                       reg = <1>;
    +               };
    +       };
    +


I believe your SoC also has a bus here.

It does but there is no active driver to manage it.

    --- /dev/null
    +++ b/arch/arm/mach-stixxxx/board-dt.c
    @@ -0,0 +1,47 @@

    +
    +void __init stih41x_l2x0_init(void)
    +{
    +       u32 way_size = 0x4;
    +       u32 aux_ctrl;
    +
    +       aux_ctrl = (0x1 << L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT) |
    +               (0x1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) |
    +               (0x1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) |
    +               (way_size << L2X0_AUX_CTRL_WAY_SIZE_SHIFT);



#include <linux/bitops.h>
Linus Walleij would write use  BIT() here

I will use BIT() macro.

    diff --git a/arch/arm/mach-stixxxx/headsmp.S
    b/arch/arm/mach-stixxxx/headsmp.S
    new file mode 100644
    index 0000000..3dd5c04
    --- /dev/null
    +++ b/arch/arm/mach-stixxxx/headsmp.S
    @@ -0,0 +1,44 @@
    +/*
    + *  arch/arm/plat-stixxxx/headsmp.S

    +       .long   pen_release


check that your SoC has no option to start/reset cpus separately.
If yes, then you shouldn't use pen_release.
We discussed this with Russel some days ago.

No, stih41x series can't reset the cores separately.

 

    diff --git a/arch/arm/mach-stixxxx/platsmp.c
    b/arch/arm/mach-stixxxx/platsmp.c
    new file mode 100644
    index 0000000..ffc40c0
    --- /dev/null
    +++ b/arch/arm/mach-stixxxx/platsmp.c
    @@ -0,0 +1,117 @@
    +/*
    + *  arch/arm/plat-stixxxx/platsmp.c


wrong.

Left over, will clean it up in next version.

    + *  arch/arm/plat-stixxxx/platsmp.c


incorrect.

Left over, will clean it up in next version.

 
    +extern struct smp_operations   stixxxx_smp_ops;
    +extern void __iomem *stixxxx_scu_base_addr;


Unused variable in this patch.

yes, I will remove stixxxx_scu_base_addr.

thanks,
srini