On Tue, Jan 17, 2012 at 3:39 PM, Catalin Marinas
[off-list ref] wrote:

On Tue, Jan 17, 2012 at 12:40:54PM +0000, Shilimkar, Santosh wrote:

quoted

Well the L2 can be configured as inner or outer, so above
alone won't work.

Boot-loader disabling L2 cache ( all caches) ?is still right thing
and that's what kernel expect.

Since the early kernel code can't be patches for A8, may be
delaying L2 enabled would work.

Ah, I missed the fact that the L2 is an inner cache on OMAP3+A8.

At least on my OMAP3 board it's not. There is L2 AUX control register
"L2 inner" bit that's always cleared here. I know outer cacheablility
bits in page table descriptors have effect here, we have tested
performace before..


-- 
Gra?vydas