On Tue, Jan 17, 2012 at 1:27 PM, Aneesh V [off-list ref] wrote:

Hi Catalin,


On Tuesday 17 January 2012 05:41 PM, Catalin Marinas wrote:

quoted

On Tue, Jan 17, 2012 at 08:54:44AM +0000, Joe Woodward wrote:

quoted

So, is the upshot of this that the kernel isn't going to be in a
position to enable the L2/outer cache on OMAP3 (due to the need for
hacky/unmaintainable code)?

Hence the bootloader/uBoot had better leave it enabled...

It could but the Linux decompressor needs to be aware and either flush
the L2 (more difficult as it doesn't have all the device information) or

Cortex-A8 is aware of L2$ and can flush it, isn't it?

quoted

set the page table attributes to outer non-cacheable (TEX[2:0] = 0b100).

If the above is right, this is not needed right?

Well the L2 can be configured as inner or outer, so above
alone won't work.

Boot-loader disabling L2 cache ( all caches)  is still right thing
and that's what kernel expect.

Since the early kernel code can't be patches for A8, may be
delaying L2 enabled would work.

But then on A15, we are back to square one since there is no
control to turn ON/OFF l2 cache. On A15 infact there are other
CP15 registers which needs to be set before MMU is enabled to
have best configuration.

So the need of this early hook is pretty much there. May be separate
CPU setup code for such cases is a possible way to go.

Basically the problem needs to be sorted out, because I already
see this is needed for A15 as well

Regards
Santosh