On Tue, 2009-09-22 at 11:14 +0530, Shilimkar, Santosh wrote:

Even though this thread is mainly focused on SMP + WA cache, can you
point out some reference which support your argument that " the
non-SMP v6/v7 processors I'm aware of only support read-allocate
caches, even if you try to force write-allocate". Mainly Cortex-a8
(ARMv7). The Cortex-A8 TRM says that it does support WBWA cache.

Please note the "I'm aware of" part. This could be limited to what I
have on my desk.

Regarding the Cortex-A8 - the 7.3.3 section in the latest TRM (Level 1
Memory System -> Memory attributes -> Normal) has a table which says for
the WBWA L1 configuration:

        This is not supported. L1 is always in the no write-allocate
        mode.

The L2 (inner cache) supports the write-allocate mode but this is a
unified cache and doesn't affect the problem we are seeing here.

-- 
Catalin