Russell King - ARM Linux wrote:

On Mon, Sep 21, 2009 at 09:10:43PM +0100, Jamie Lokier wrote:

quoted

And here's a little something:

http://www.mail-archive.com/aufs-users at lists.sourceforge.net/msg02093.html

It's about MIPS, but has an awful lot of things in common with the bug
being discussed in this thread: dynamic linker, constants embedded in
the code, using mprotect rx->rw->rx, missing I-cache flush, only
affects COW, copy_user_highpage(), is worked around by switching the
cache from write-back to write-through...

Useful?

Depends.  ARMv7 has the requirement that memory is not mapped in using
different cache settings (we already violate that, and ARM Ltd's aware
of that, but no one yet knows how to solve it in Linux.)

I think so far the hardware can cope with this as long as you don't 
access both mappings at the same time (they would need at least a DSB 
between accesses with different mappings). If a new CPU requires this 
strict rule to be enforced, the solution I see is a hardware one - ACP 
(ARM's Accelerator Coherency Port) - where we get everything, including 
DMA memory, mapped cached.

-- 
Catalin