On Wed, Oct 05, 2022 at 01:31:28AM +0000, Andrew Cooper wrote:

On 29/09/2022 23:29, Rick Edgecombe wrote:

quoted

From: Yu-cheng Yu <redacted>

Processors sometimes directly create Write=0,Dirty=1 PTEs.

Do they? (Rhetorical)

Yes, this is a relevant anecdote for why CET isn't available on pre-TGL
parts, but it one of the more wrong things to have as the first sentence
of this commit message.

The point you want to express is that under the CET-SS spec, R/O+Dirty
has a new meaning as type=shstk, so stop using this bit combination for
existing mappings.

I'm not even sure it's relevant to note that CET capable processors can
set D on a R/O mapping, because that depends on !CR0.WP which in turn
prohibits CR4.CET being enabled.

Whilst I agree that the Changelog is 'suboptimal' -- I do think it might
be good to mention how we ended up at the current state where we
explicitly set this non-sensical W=0,D=1 state.

Looking at the git history this seems to be a bit of a hysterical
accident, not something done on purpose to 'optimize' for these weird
CPUs.