Re: [PATCHv6 06/10] node: Add memory-side caching attributes
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From: Brice Goglin <hidden>
Date: 2019-02-22 10:12:43
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linux-acpi, linux-mm, lkml
Le 14/02/2019 à 18:10, Keith Busch a écrit :
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System memory may have caches to help improve access speed to frequently requested address ranges. While the system provided cache is transparent to the software accessing these memory ranges, applications can optimize their own access based on cache attributes. Provide a new API for the kernel to register these memory-side caches under the memory node that provides it. The new sysfs representation is modeled from the existing cpu cacheinfo attributes, as seen from /sys/devices/system/cpu/<cpu>/cache/. Unlike CPU cacheinfo though, the node cache level is reported from the view of the memory. A higher level number is nearer to the CPU, while lower levels are closer to the last level memory. The exported attributes are the cache size, the line size, associativity, and write back policy, and add the attributes for the system memory caches to sysfs stable documentation. Signed-off-by: Keith Busch <redacted> --- Documentation/ABI/stable/sysfs-devices-node | 35 +++++++ drivers/base/node.c | 151 ++++++++++++++++++++++++++++ include/linux/node.h | 34 +++++++ 3 files changed, 220 insertions(+)diff --git a/Documentation/ABI/stable/sysfs-devices-node b/Documentation/ABI/stable/sysfs-devices-node index cd64b62152ba..5c88cb9ca14e 100644 --- a/Documentation/ABI/stable/sysfs-devices-node +++ b/Documentation/ABI/stable/sysfs-devices-node@@ -143,3 +143,38 @@ Contact: Keith Busch <keith.busch@intel.com> Description: This node's write latency in nanoseconds when access from nodes found in this class's linked initiators. + +What: /sys/devices/system/node/nodeX/memory_side_cache/indexY/ +Date: December 2018 +Contact: Keith Busch <keith.busch@intel.com> +Description: + The directory containing attributes for the memory-side cache + level 'Y'. + + The caches associativity: 0 for direct mapped, non-zero if +What: /sys/devices/system/node/nodeX/memory_side_cache/indexY/associativity +Date: December 2018 +Contact: Keith Busch <keith.busch@intel.com> +Description: + The caches associativity: 0 for direct mapped, non-zero if + indexed. + +What: /sys/devices/system/node/nodeX/memory_side_cache/indexY/line_size +Date: December 2018 +Contact: Keith Busch <keith.busch@intel.com> +Description: + The number of bytes accessed from the next cache level on a + cache miss. + +What: /sys/devices/system/node/nodeX/memory_side_cache/indexY/size +Date: December 2018 +Contact: Keith Busch <keith.busch@intel.com> +Description: + The size of this memory side cache in bytes.
Hello Keith, CPU-side cache size is reported in kilobytes: $ cat /sys/devices/system/cpu/cpu0/cache/index*/size 32K 32K 256K 4096K Can you do the same of memory-side caches instead of reporting bytes? Thanks Brice