Re: [PATCH v1 1/5] dmaengine: arm-dma350: Fix source trigger bit
From: sashiko-bot@kernel.org
Date: 2026-09-07 03:41:54
Also in:
linux-devicetree
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider: Pre-existing issues: - [High] The driver ignores the return value of `dma_set_mask_and_coherent()`, which can lead to silent memory corruption if the requested DMA mask is unsupported. -- commit c925d144b95da8512ff2006d79c7add5a368be10 Author: Jelly Jia [off-list ref] Subject: dmaengine: arm-dma350: Fix source trigger bit This commit corrects the bit used for the source trigger enable in the CH_CTRL register. It changes the value from bit 26 to the proper bit 25 to avoid inadvertently enabling the destination trigger input. This prevents silent failures in transfers that wait for a peripheral request.
quoted hunk ↗ jump to hunk
diff --git a/drivers/dma/arm-dma350.c b/drivers/dma/arm-dma350.c index 09403aca8bb06..4e17130de6c87 100644 --- a/drivers/dma/arm-dma350.c +++ b/drivers/dma/arm-dma350.c@@ -63,7 +63,7 @@ #define CH_CTRL 0x0c #define CH_CTRL_USEDESTRIGIN BIT(26) -#define CH_CTRL_USESRCTRIGIN BIT(26) +#define CH_CTRL_USESRCTRIGIN BIT(25) #define CH_CTRL_DONETYPE GENMASK(23, 21) #define CH_CTRL_REGRELOADTYPE GENMASK(20, 18) #define CH_CTRL_XTYPE GENMASK(11, 9)
While reviewing this, I noticed a pre-existing issue in the device probe
path:
drivers/dma/arm-dma350.c:d350_probe() {
...
reg = readl_relaxed(base + DMAINFO + DMA_BUILDCFG0);
nchan = FIELD_GET(DMA_CFG_NUM_CHANNELS, reg) + 1;
dw = 1 << FIELD_GET(DMA_CFG_DATA_WIDTH, reg);
aw = FIELD_GET(DMA_CFG_ADDR_WIDTH, reg) + 1;
dma_set_mask_and_coherent(dev, DMA_BIT_MASK(aw));
coherent = device_get_dma_attr(dev) == DEV_DMA_COHERENT;
...
}
[Severity: High]
This is a pre-existing issue, but should the return value of
dma_set_mask_and_coherent() be checked and handled here?
If the requested mask is rejected by the architecture or IOMMU during
device probe, couldn't the system fall back to a default mask (typically
32-bit)?
If the dynamically read hardware address width (aw) is less than 32, the
kernel might map memory addresses that the hardware cannot reach. Could
this lead to address truncation by the hardware and silent memory
corruption during DMA transfers?
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260907033404.596839-1-Jelly.Jia@cixtech.com?part=1