[PATCH v4] dmaengine: dw-axi-dmac: convert to clk bulk APIs
From: Li Youhong <hidden>
Date: 2026-09-03 01:55:04
Subsystem:
dma generic offload engine subsystem, synopsys designware axi dmac driver, the rest · Maintainers:
Vinod Koul, Eugeniy Paltsev, Linus Torvalds
From: Li Youhong <redacted>
axi_dma_resume() enables cfgr_clk then core_clk. If enabling
core_clk fails, return without disabling cfgr_clk, leaking the
already-enabled clock.
Switch both clocks to the clk bulk helpers so prepare/enable
failures roll back automatically, and update probe/remove/
suspend/resume accordingly.
In dw_remove(), check clk_bulk_prepare_enable(). On failure skip
MMIO and the matching disable to avoid unbalanced clk disable;
always continue with IRQ/OF/tasklet teardown.
Fixes: 1fe20f1b8454 ("dmaengine: Introduce DW AXI DMAC driver")
Suggested-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Li Youhong <redacted>
---
.../dma/dw-axi-dmac/dw-axi-dmac-platform.c | 42 +++++++++----------
drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 4 +-
2 files changed, 22 insertions(+), 24 deletions(-)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index eebed2474210..413be7dce5fc 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c@@ -1320,8 +1320,7 @@ static int axi_dma_suspend(struct axi_dma_chip *chip) axi_dma_irq_disable(chip); axi_dma_disable(chip); - clk_disable_unprepare(chip->core_clk); - clk_disable_unprepare(chip->cfgr_clk); + clk_bulk_disable_unprepare(DW_AXI_DMA_MAX_CLKS, chip->clks); return 0; }
@@ -1330,11 +1329,7 @@ static int axi_dma_resume(struct axi_dma_chip *chip) { int ret; - ret = clk_prepare_enable(chip->cfgr_clk); - if (ret < 0) - return ret; - - ret = clk_prepare_enable(chip->core_clk); + ret = clk_bulk_prepare_enable(DW_AXI_DMA_MAX_CLKS, chip->clks); if (ret < 0) return ret;
@@ -1524,13 +1519,11 @@ static int dw_probe(struct platform_device *pdev) chip->dw->hdata->use_cfg2 = !!(flags & AXI_DMA_FLAG_USE_CFG2); - chip->core_clk = devm_clk_get(chip->dev, "core-clk"); - if (IS_ERR(chip->core_clk)) - return PTR_ERR(chip->core_clk); - - chip->cfgr_clk = devm_clk_get(chip->dev, "cfgr-clk"); - if (IS_ERR(chip->cfgr_clk)) - return PTR_ERR(chip->cfgr_clk); + chip->clks[0].id = "cfgr-clk"; + chip->clks[1].id = "core-clk"; + ret = devm_clk_bulk_get(chip->dev, DW_AXI_DMA_MAX_CLKS, chip->clks); + if (ret) + return ret; ret = parse_device_properties(chip); if (ret)
@@ -1640,19 +1633,24 @@ static void dw_remove(struct platform_device *pdev) struct dw_axi_dma *dw = chip->dw; struct axi_dma_chan *chan, *_chan; u32 i; + int ret; /* Enable clk before accessing to registers */ - clk_prepare_enable(chip->cfgr_clk); - clk_prepare_enable(chip->core_clk); - axi_dma_irq_disable(chip); - for (i = 0; i < dw->hdata->nr_channels; i++) { - axi_chan_disable(&chip->dw->chan[i]); - axi_chan_irq_disable(&chip->dw->chan[i], DWAXIDMAC_IRQ_ALL); + ret = clk_bulk_prepare_enable(DW_AXI_DMA_MAX_CLKS, chip->clks); + if (ret) + dev_err(&pdev->dev, "Failed to enable clocks\n"); + else { + axi_dma_irq_disable(chip); + for (i = 0; i < dw->hdata->nr_channels; i++) { + axi_chan_disable(&chip->dw->chan[i]); + axi_chan_irq_disable(&chip->dw->chan[i], DWAXIDMAC_IRQ_ALL); + } + axi_dma_disable(chip); } - axi_dma_disable(chip); pm_runtime_disable(chip->dev); - axi_dma_suspend(chip); + if (!ret) + axi_dma_suspend(chip); for (i = 0; i < DMAC_MAX_CHANNELS; i++) if (chip->irq[i] > 0)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
index 67cc199e24d1..681dd6162baf 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h@@ -21,6 +21,7 @@ #define DMAC_MAX_CHANNELS 32 #define DMAC_MAX_MASTERS 2 #define DMAC_MAX_BLK_SIZE 0x200000 +#define DW_AXI_DMA_MAX_CLKS 2 struct dw_axi_dma_hcfg { u32 nr_channels;
@@ -69,8 +70,7 @@ struct axi_dma_chip { int irq[DMAC_MAX_CHANNELS]; void __iomem *regs; void __iomem *apb_regs; - struct clk *core_clk; - struct clk *cfgr_clk; + struct clk_bulk_data clks[DW_AXI_DMA_MAX_CLKS]; struct dw_axi_dma *dw; };
--
2.25.1