Re: [PATCH] [RFC] dmaengine: add fifo_size member
From: Jon Hunter <jonathanh@nvidia.com>
Date: 2019-06-06 16:53:26
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On 06/06/2019 17:44, Dmitry Osipenko wrote:
06.06.2019 19:32, Jon Hunter пишет:quoted
On 06/06/2019 16:18, Dmitry Osipenko wrote: ...quoted
quoted
quoted
If I understood everything correctly, the FIFO buffer is shared among all of the ADMA clients and hence it should be up to the ADMA driver to manage the quotas of the clients. So if there is only one client that uses ADMA at a time, then this client will get a whole FIFO buffer, but once another client starts to use ADMA, then the ADMA driver will have to reconfigure hardware to split the quotas.The FIFO quotas are managed by the ADMAIF driver (does not exist in mainline currently but we are working to upstream this) because it is this device that owns and needs to configure the FIFOs. So it is really a means to pass the information from the ADMAIF to the ADMA.So you'd want to reserve a larger FIFO for an audio channel that has a higher audio rate since it will perform reads more often. You could also prioritize one channel over the others, like in a case of audio call for example. Is the shared buffer smaller than may be needed by clients in a worst case scenario? If you could split the quotas statically such that each client won't ever starve, then seems there is no much need in the dynamic configuration.Actually, this is still very much relevant for the static case. Even if we defined a static configuration of the FIFO mapping in the ADMAIF driver we still need to pass this information to the ADMA. I don't really like the idea of having it statically defined in two different drivers.Ah, so you need to apply the same configuration in two places. Correct? Are ADMAIF and ADMA really two different hardware blocks? Or you artificially decoupled the ADMA driver?
These are two different hardware modules with their own register sets. Yes otherwise, it would be a lot simpler! Jon -- nvpublic