[PATCH 5.12 192/677] arm64: dts: qcom: sm8250: Fix level triggered PMU interrupt polarity
From: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Date: 2021-05-12 18:38:10
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arm/qualcomm mailing list, arm/qualcomm support, the rest · Maintainers:
Bjorn Andersson, Konrad Dybcio, Linus Torvalds
From: Sai Prakash Ranjan <redacted>
[ Upstream commit 93138ef5ac923b10f81575d35dbcb83136cbfc40 ]
As per interrupt documentation for SM8250 SoC, the polarity
for level triggered PMU interrupt is low, fix this.
Fixes: 60378f1a171e ("arm64: dts: qcom: sm8250: Add sm8250 dts file")
Signed-off-by: Sai Prakash Ranjan <redacted>
Link: https://lore.kernel.org/r/96680a1c6488955c9eef7973c28026462b2a4ec0.1613468366.git.saiprakash.ranjan@codeaurora.org (local)
Signed-off-by: Bjorn Andersson <redacted>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index 947e1accae3a..1864c459a563 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi@@ -279,7 +279,7 @@ pmu { compatible = "arm,armv8-pmuv3"; - interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; }; psci {
--
2.30.2