Thread (695 messages) 695 messages, 11 authors, 2021-05-13
STALE1842d

[PATCH 5.12 255/677] memory: pl353: fix mask of ECC page_size config register

From: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Date: 2021-05-12 18:31:51
Also in: lkml
Subsystem: arm primecell pl35x smc driver, memory controller drivers, the rest · Maintainers: Miquel Raynal, Krzysztof Kozlowski, Linus Torvalds

From: gexueyuan <redacted>

[ Upstream commit 25dcca7fedcd4e31cb368ad846bfd738c0c6307c ]

The mask for page size of ECC Configuration Register should be 0x3,
according to  the datasheet of PL353 smc.

Fixes: fee10bd22678 ("memory: pl353: Add driver for arm pl353 static memory controller")
Signed-off-by: gexueyuan <redacted>
Link: https://lore.kernel.org/r/20210331031056.5326-1-gexueyuan@gmail.com (local)
Signed-off-by: Krzysztof Kozlowski <redacted>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 drivers/memory/pl353-smc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/memory/pl353-smc.c b/drivers/memory/pl353-smc.c
index 3b5b1045edd9..9c0a28416777 100644
--- a/drivers/memory/pl353-smc.c
+++ b/drivers/memory/pl353-smc.c
@@ -63,7 +63,7 @@
 /* ECC memory config register specific constants */
 #define PL353_SMC_ECC_MEMCFG_MODE_MASK	0xC
 #define PL353_SMC_ECC_MEMCFG_MODE_SHIFT	2
-#define PL353_SMC_ECC_MEMCFG_PGSIZE_MASK	0xC
+#define PL353_SMC_ECC_MEMCFG_PGSIZE_MASK	0x3
 
 #define PL353_SMC_DC_UPT_NAND_REGS	((4 << 23) |	/* CS: NAND chip */ \
 				 (2 << 21))	/* UpdateRegs operation */
-- 
2.30.2


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