[PATCH net-next v3 8/9] net: stmmac: mediatek: add support for TX clock output enable feature
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HOTtoday
From: Louis-Alexis Eyraud <hidden>
Date: 2026-10-16 10:32:38
Also in:
linux-arm-kernel, linux-devicetree, linux-mediatek, lkml
Subsystem:
networking drivers, stmmac ethernet driver, the rest · Maintainers:
Andrew Lunn, "David S. Miller", Eric Dumazet, Jakub Kicinski, Paolo Abeni, Maxime Chevallier, Linus Torvalds
The MT8189 SoC has in the Ethernet control 0 register from the peripheral configuration (pericfg) an additional bit to enable the TX clock signal output. In preparation of MT8189 SoC support, add its definition, use in the mt8195_set_interface callback, and a support flag in the platform data. Signed-off-by: Louis-Alexis Eyraud <redacted> --- drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c | 7 +++++++ 1 file changed, 7 insertions(+)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c
index 4b2d5280f703..147e217b8662 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c@@ -44,6 +44,9 @@ #define MT2712_RGMII_DLY_TXC_STAGE_DIV 550 /* 550ps per stage */ #define MT2712_RGMII_DLY_TXC_MAX 17600 /* 32 x 550ps */ +/* Peri Configuration register for mt8189 */ +#define MT8189_CTRL0_TXC_OUT_OP_EN BIT(20) + /* Peri Configuration register for mt8195 */ #define MT8195_PERI_ETH_CTRL_OFFSET 0xFD0
@@ -119,6 +122,7 @@ struct mediatek_dwmac_variant { u16 rx_rgmii_delay_stage_div; u16 tx_rgmii_delay_stage_div; u8 dma_bit_mask; + bool mac_txclk_out_en; }; /* list of clocks required for mac */
@@ -299,6 +303,9 @@ static int mt8195_set_interface(struct mediatek_dwmac_plat_data *plat, /* MT8195 only support external PHY */ intf_val |= MT8195_EXT_PHY_MODE; + if (plat->variant->mac_txclk_out_en) + intf_val |= MT8189_CTRL0_TXC_OUT_OP_EN; + regmap_write(plat->peri_regmap, reg_offset + MT8195_PERI_ETH_CTRL0, intf_val);
--
2.56.0