[PATCH net-next v3 6/9] net: stmmac: mediatek: add PERI_ETH_CTRLx register offset in platform data
flat view
COOLING4d
REVIEWED: 1 (1M)
From: Louis-Alexis Eyraud <hidden>
Date: 2026-10-16 10:32:22
Also in:
linux-arm-kernel, linux-devicetree, linux-mediatek, lkml
Subsystem:
networking drivers, stmmac ethernet driver, the rest · Maintainers:
Andrew Lunn, "David S. Miller", Eric Dumazet, Jakub Kicinski, Paolo Abeni, Maxime Chevallier, Linus Torvalds
Revision v3 of 3 in this series; 1 review trailer (1 from subsystem maintainers).
Revisions (3)
- v1 [diff vs current]
- v2 [diff vs current]
- v3 current
In preparation of newer SoC support, that use like MT8195 the Ethernet control registers from the peripheral configuration syscon but at a different base offset, add a new base offset in the variant platform data to access the PERI_ETH_CTRLx registers and use it in implemented methods. Reviewed-by: Maxime Chevallier <maxime.chevallier@bootlin.com> Signed-off-by: Louis-Alexis Eyraud <redacted> --- .../net/ethernet/stmicro/stmmac/dwmac-mediatek.c | 26 ++++++++++++++++------ 1 file changed, 19 insertions(+), 7 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c
index cb5bda53edb9..7dd46cd5a49e 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c@@ -45,7 +45,9 @@ #define MT2712_RGMII_DLY_TXC_MAX 17600 /* 32 x 550ps */ /* Peri Configuration register for mt8195 */ -#define MT8195_PERI_ETH_CTRL0 0xFD0 +#define MT8195_PERI_ETH_CTRL_OFFSET 0xFD0 + +#define MT8195_PERI_ETH_CTRL0 0x0 #define MT8195_RMII_CLK_SRC_INTERNAL BIT(28) #define MT8195_RMII_CLK_SRC_RXC BIT(27) #define MT8195_ETH_INTF_SEL GENMASK(26, 24)
@@ -55,7 +57,7 @@ #define MT8195_DLY_GTXC_ENABLE BIT(5) #define MT8195_DLY_GTXC_STAGES GENMASK(4, 0) -#define MT8195_PERI_ETH_CTRL1 0xFD4 +#define MT8195_PERI_ETH_CTRL1 0x4 #define MT8195_DLY_RXC_INV BIT(25) #define MT8195_DLY_RXC_ENABLE BIT(18) #define MT8195_DLY_RXC_STAGES GENMASK(17, 13)
@@ -63,7 +65,7 @@ #define MT8195_DLY_TXC_ENABLE BIT(5) #define MT8195_DLY_TXC_STAGES GENMASK(4, 0) -#define MT8195_PERI_ETH_CTRL2 0xFD8 +#define MT8195_PERI_ETH_CTRL2 0x8 #define MT8195_DLY_RMII_RXC_INV BIT(25) #define MT8195_DLY_RMII_RXC_ENABLE BIT(18) #define MT8195_DLY_RMII_RXC_STAGES GENMASK(17, 13)
@@ -106,6 +108,7 @@ struct mediatek_dwmac_variant { const char * const *clk_list; int num_clks; + u32 peri_eth_ctrl_offset; u32 rx_delay_max; u32 tx_delay_max; u16 rx_rmii_delay_stage_div;
@@ -281,6 +284,7 @@ static int mt8195_set_interface(struct mediatek_dwmac_plat_data *plat, u8 phy_intf_sel) { u32 intf_val = FIELD_PREP(MT8195_ETH_INTF_SEL, phy_intf_sel); + u32 reg_offset = plat->variant->peri_eth_ctrl_offset; if (phy_intf_sel == PHY_INTF_SEL_RMII) { if (plat->rmii_clk_from_mac)
@@ -292,7 +296,9 @@ static int mt8195_set_interface(struct mediatek_dwmac_plat_data *plat, /* MT8195 only support external PHY */ intf_val |= MT8195_EXT_PHY_MODE; - regmap_write(plat->peri_regmap, MT8195_PERI_ETH_CTRL0, intf_val); + regmap_write(plat->peri_regmap, + reg_offset + MT8195_PERI_ETH_CTRL0, + intf_val); return 0; }
@@ -302,6 +308,7 @@ static int mt8195_set_delay(struct mediatek_dwmac_plat_data *plat) u16 rx_delay_stage_div = plat->variant->rx_rgmii_delay_stage_div; u16 tx_delay_stage_div = plat->variant->tx_rgmii_delay_stage_div; struct mac_delay_struct *mac_delay = &plat->mac_delay; + u32 reg_offset = plat->variant->peri_eth_ctrl_offset; u32 rx_delay_stage_val; u32 tx_delay_stage_val; u32 gtxc_delay_val = 0;
@@ -407,14 +414,18 @@ static int mt8195_set_delay(struct mediatek_dwmac_plat_data *plat) } regmap_update_bits(plat->peri_regmap, - MT8195_PERI_ETH_CTRL0, + reg_offset + MT8195_PERI_ETH_CTRL0, MT8195_RGMII_TXC_PHASE_CTRL | MT8195_DLY_GTXC_INV | MT8195_DLY_GTXC_ENABLE | MT8195_DLY_GTXC_STAGES, gtxc_delay_val); - regmap_write(plat->peri_regmap, MT8195_PERI_ETH_CTRL1, delay_val); - regmap_write(plat->peri_regmap, MT8195_PERI_ETH_CTRL2, rmii_delay_val); + regmap_write(plat->peri_regmap, + reg_offset + MT8195_PERI_ETH_CTRL1, + delay_val); + regmap_write(plat->peri_regmap, + reg_offset + MT8195_PERI_ETH_CTRL2, + rmii_delay_val); return 0; }
@@ -429,6 +440,7 @@ static const struct mediatek_dwmac_variant mt8195_gmac_variant = { .rx_rgmii_delay_stage_div = MT8195_DLY_RXC_STAGE_DIV, .tx_rgmii_delay_stage_div = MT8195_DLY_TXC_STAGE_DIV, .dma_bit_mask = 35, + .peri_eth_ctrl_offset = MT8195_PERI_ETH_CTRL_OFFSET, }; static int mediatek_dwmac_config_dt(struct mediatek_dwmac_plat_data *plat)
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2.56.0