On Sat, Oct 10, 2026 at 10:18 PM Nicolai Buchwitz [off-list ref] wrote:
I dug a bit deeper on a CM4: AFAIU the MDC runs off the GISB clock,
which the firmware sets to 200 MHz (CPRMAN 0x1d8, PLLD_PER 750 MHz /
3.75). Bumping that divider to 4.0 at runtime moves the MDIO busy time
by exactly the same ratio, so that's the one. The 250 MHz you have in
mind is genet250 / genet125, the RGMII side, a different generator.
So instead of a fixed clock or a compatible match this could just be
BCM2711_CLOCK_GISB in clk-bcm2835 (critical, firmware owns it) and
clocks = <&clocks BCM2711_CLOCK_GISB> on the mdio node. I can send that
if it helps.
Thank you very much for looking into this. I think this would solve
the problem from my end.
Let me just confirm how I would need to adapt my patch with that fix:
in the pdata branch of the probe, I would call devm_clk_get_optional
to find the clock on the mdio node, falling back to pdata->clk. I
would still add the chip-specific compatible string because the number
of MDC periods has only been measured on that specific hardware.
James