Re: [PATCH net-next 3/4] dt-bindings: net: qcom,ipq9574-ppe: Add IPQ5332 support

On Mon, Oct 05, 2026 at 05:29:14PM +0200, Til Kaiser wrote:

IPQ5332 uses the same PPE architecture as IPQ9574, but has two front
panel ports instead of six and four interconnect paths instead of seven.

Add the qcom,ipq5332-ppe compatible and constrain the interconnects
and port nodes per SoC: IPQ5332 takes four interconnects and only
ethernet-port@1 and ethernet-port@2, while IPQ9574 keeps seven
interconnects.

The PPE core, EDMA and MAC clock functions are shared, but IPQ5332 also
needs the GCC IM sleep clock. The PPE core uses one reset and each MAC
uses three resets on both SoCs. IPQ5332 EDMA needs separate system and
configuration resets; IPQ9574 uses one combined reset. Constrain the
clock and reset counts accordingly. Keep EDMA resets positional, with
the system reset first and the configuration reset second on IPQ5332,
consistent with the existing unnamed IPQ9574 reset.

IPQ5332 EDMA has 24 TX/completion rings, 16 RX descriptor rings and eight
RX fill rings, so the full EDMA interrupt set comprises 49 interrupts.
Constrain the interrupt counts and ring names per SoC as well.

The IPQ5332 clock and reset functions are described by Qualcomm's NSSCC

How is clock relevant to this device? This is PPE, no?

driver submission. Its sleep clock is also listed in Qualcomm's
PPE DTS submission. The ring limits come from QSDK 14.0.1595.1665,
qca-nss-dp hal/soc_ops/ipq53xx/nss_ipq53xx.h.

Link: https://lore.kernel.org/r/20240829082830.56959-7-quic_varada@quicinc.com (local)
Link: https://lore.kernel.org/r/20240110112059.2498-3-quic_luoj@quicinc.com (local)

I do not understand how these clock patches are relevant here.

Drop links and paragraph not relevant to this code.

With this:

Reviewed-by: Krzysztof Kozlowski <redacted>

Best regards,
Krzysztof