[PATCH net v3 1/4] dpll: zl3073x: reject output frequencies with too small divisor
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COOLING8d
SUPERSEDED
From: Ivan Vecera <ivecera@redhat.com>
Date: 2026-10-06 15:31:30
Also in:
lkml
Subsystem:
dpll subsystem, microchip zl3073x driver, the rest · Maintainers:
Vadim Fedorenko, Arkadiusz Kubalewski, Jiri Pirko, Ivan Vecera, Min Li, Linus Torvalds
Revision v3 of 3 in this series.
Revisions (3)
- v3 current
- v4 [diff vs current]
- v5 [diff vs current]
The output divider has to be at least 2. In N-pin divide mode the
per-output divider must be 2 or more and the N-pin is divided once more
(also by 2 or more), so the N-pin needs an effective divisor of at least
4.
zl3073x_pin_check_freq() only checked that an output frequency divides the
synth frequency, so it accepted frequencies that would require a smaller
divisor. Reject them: require a divisor of at least 2 for normal outputs
and the P-pin of N-divided outputs, and 4 for the N-pin. Also reject a
zero frequency, which would otherwise divide by zero.
Fixes: a99a9f0ebdaa ("dpll: zl3073x: Read DPLL types and pin properties from system firmware")
Signed-off-by: Ivan Vecera <ivecera@redhat.com>
---
drivers/dpll/zl3073x/prop.c | 29 ++++++++++++++++++++++-------
1 file changed, 22 insertions(+), 7 deletions(-)
diff --git a/drivers/dpll/zl3073x/prop.c b/drivers/dpll/zl3073x/prop.c
index ac9d41d0f978..a4bdc3878590 100644
--- a/drivers/dpll/zl3073x/prop.c
+++ b/drivers/dpll/zl3073x/prop.c@@ -22,7 +22,8 @@ * The function checks the given frequency is valid for the device. For input * pins it checks that the frequency can be factorized using supported base * frequencies. For output pins it checks that the frequency divides connected - * synth frequency without remainder. + * synth frequency without remainder and that the resulting divisor is within + * the range supported by the hardware. * * Return: true if the frequency is valid, false if not. */
@@ -30,7 +31,7 @@ static bool zl3073x_pin_check_freq(struct zl3073x_dev *zldev, enum dpll_pin_direction dir, u8 id, u64 freq) { - if (freq > U32_MAX) + if (!freq || freq > U32_MAX) goto err_inv_freq; if (dir == DPLL_PIN_DIRECTION_INPUT) {
@@ -41,18 +42,32 @@ zl3073x_pin_check_freq(struct zl3073x_dev *zldev, enum dpll_pin_direction dir, if (rc) goto err_inv_freq; } else { - u32 synth_freq; - u8 out, synth; + const struct zl3073x_out *out; + u32 synth_freq, div, min_div, rem; + u8 out_id, synth; /* Get output pin synthesizer */ - out = zl3073x_output_pin_out_get(id); - synth = zl3073x_dev_out_synth_get(zldev, out); + out_id = zl3073x_output_pin_out_get(id); + synth = zl3073x_dev_out_synth_get(zldev, out_id); /* Get synth frequency */ synth_freq = zl3073x_dev_synth_freq_get(zldev, synth); /* Check the frequency divides synth frequency */ - if (synth_freq % (u32)freq) + div = div_u64_rem(synth_freq, freq, &rem); + if (rem) + goto err_inv_freq; + + /* The output divisor has to be at least 2. For the N-pin of an + * N-divided output the effective divisor also includes the N + * divider (>= 2), so the minimum is 4. + */ + out = zl3073x_out_state_get(zldev, out_id); + if (zl3073x_out_is_ndiv(out) && zl3073x_is_n_pin(id)) + min_div = 4; + else + min_div = 2; + if (div < min_div) goto err_inv_freq; }
--
2.55.0