Re: [PATCH net-next v9 03/15] dpll: add basic SiTime SiT9531x support

On 9/17/26 10:42 AM, Ivan Vecera wrote:

quoted

+const struct regmap_config sit9531x_regmap_config = {
+	.reg_bits = 8,
+	.val_bits = 8,
+	.max_register = SIT9531X_RANGE_OFFSET +
+			(SIT9531X_NUM_PAGES * SIT9531X_PAGE_SIZE) - 1,
+	.ranges = &sit9531x_regmap_range,
+	.num_ranges = 1,
+	.cache_type = REGCACHE_NONE,
+};

Couldn't it be useful to cache at least page selector register or is it 
volatile? I remember from zl3073x history that page selector caching 
helped a lot to reduce number of i2c transactions.

It is not volatile, and caching it is worth doing. This is in v10.

The regmap config now marks every register in the map volatile except
the page selector, so the selector is the only cached register and
regmap stops rewriting it when consecutive accesses stay on the same
page. Most of this driver's access patterns touch several registers
from one page in a row, so that removes the selector write that used to
precede each of them.

Everything else has to stay volatile. The status bits, the TDC phase
measurement, the frequency-offset taps and the divider readbacks all
change underneath the driver, and a cached copy of any of them would
hand userspace a stale measurement.

Thanks for the zl3073x pointer. Having the same decision already made
in-tree, for the same reason, is what made this easy to justify. Patch
3 in v10 carries

  Suggested-by: Ivan Vecera [off-list ref]

v10 is posted:
https://lore.kernel.org/netdev/20260921201108.42676-1-arouhi@sitime.com/ (local)

Thanks,
Ali