[PATCH v3 3/6] bus: mhi: host: Add support for 64bit register reads and writes
From: Krishna Chaitanya Chundru <hidden>
Date: 2026-09-17 07:08:43
Also in:
linux-arm-msm, lkml
Subsystem:
mhi bus, the rest · Maintainers:
Manivannan Sadhasivam, Linus Torvalds
Some mhi registers are of 64 bit size, instead of reading high value and low value separately provide a new function op to read & write to 64 bit register. Signed-off-by: Krishna Chaitanya Chundru <redacted> --- drivers/bus/mhi/host/internal.h | 4 ++++ drivers/bus/mhi/host/main.c | 13 +++++++++++++ include/linux/mhi.h | 6 ++++++ 3 files changed, 23 insertions(+)
diff --git a/drivers/bus/mhi/host/internal.h b/drivers/bus/mhi/host/internal.h
index ca50961769fa..bb96dfffabb6 100644
--- a/drivers/bus/mhi/host/internal.h
+++ b/drivers/bus/mhi/host/internal.h@@ -386,6 +386,8 @@ void mhi_db_brstmode_disable(struct mhi_controller *mhi_cntrl, dma_addr_t db_val); int __must_check mhi_read_reg(struct mhi_controller *mhi_cntrl, void __iomem *base, u32 offset, u32 *out); +int __must_check mhi_read_reg64(struct mhi_controller *mhi_cntrl, + void __iomem *base, u32 offset, u64 *out); int __must_check mhi_read_reg_field(struct mhi_controller *mhi_cntrl, void __iomem *base, u32 offset, u32 mask, u32 *out);
@@ -394,6 +396,8 @@ int __must_check mhi_poll_reg_field(struct mhi_controller *mhi_cntrl, u32 val, u32 delayus, u32 timeout_ms); void mhi_write_reg(struct mhi_controller *mhi_cntrl, void __iomem *base, u32 offset, u32 val); +void __maybe_unused mhi_write_reg64(struct mhi_controller *mhi_cntrl, void __iomem *base, + u32 offset, u64 val); int __must_check mhi_write_reg_field(struct mhi_controller *mhi_cntrl, void __iomem *base, u32 offset, u32 mask, u32 val);
diff --git a/drivers/bus/mhi/host/main.c b/drivers/bus/mhi/host/main.c
index 4d458396233a..bfeb5cf53448 100644
--- a/drivers/bus/mhi/host/main.c
+++ b/drivers/bus/mhi/host/main.c@@ -67,6 +67,19 @@ void mhi_write_reg(struct mhi_controller *mhi_cntrl, void __iomem *base, mhi_cntrl->write_reg(mhi_cntrl, base + offset, val); } +int __must_check mhi_read_reg64(struct mhi_controller *mhi_cntrl, + void __iomem *base, u32 offset, u64 *out) +{ + return mhi_cntrl->read_reg64(mhi_cntrl, base + offset, out); +} +EXPORT_SYMBOL_GPL(mhi_read_reg64); + +void __maybe_unused mhi_write_reg64(struct mhi_controller *mhi_cntrl, void __iomem *base, + u32 offset, u64 val) +{ + mhi_cntrl->write_reg64(mhi_cntrl, base + offset, val); +} + int __must_check mhi_write_reg_field(struct mhi_controller *mhi_cntrl, void __iomem *base, u32 offset, u32 mask, u32 val)
diff --git a/include/linux/mhi.h b/include/linux/mhi.h
index e994ca4f9810..3dc1844222cd 100644
--- a/include/linux/mhi.h
+++ b/include/linux/mhi.h@@ -374,6 +374,8 @@ struct mhi_controller_config { * @unmap_single: CB function to destroy TRE buffer * @read_reg: Read a MHI register via the physical link (required) * @write_reg: Write a MHI register via the physical link (required) + * @read_reg64: Read a 64 bit MHI register via the physical link (optional) + * @write_reg64: Write a 64 bit MHI register via the physical link (optional) * @reset: Controller specific reset function (optional) * @edl_trigger: CB function to trigger EDL mode (optional) * @buffer_len: Bounce buffer length
@@ -461,6 +463,10 @@ struct mhi_controller { u32 *out); void (*write_reg)(struct mhi_controller *mhi_cntrl, void __iomem *addr, u32 val); + int (*read_reg64)(struct mhi_controller *mhi_cntrl, void __iomem *addr, + u64 *out); + void (*write_reg64)(struct mhi_controller *mhi_cntrl, void __iomem *addr, + u64 val); void (*reset)(struct mhi_controller *mhi_cntrl); int (*edl_trigger)(struct mhi_controller *mhi_cntrl);
--
2.34.1