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Luiz Angelo Daros de Luca
luizluca@gmail.com
Em qui., 3 de set. de 2026 às 09:24, Andrew Lunn [off-list ref] escreveu:
On Thu, Sep 03, 2026 at 11:22:11AM +0200, Oleksij Rempel wrote:
quoted
Add EEE support on the integrated-PHY ports, controllable per port via
ethtool.
The integrated PHYs have no MMD registers; their EEE registers live in the
switch's OCP space. phylib accesses EEE as MMD registers, so add
phy_{read,write}_c45 realtek_ops that map those MMD accesses onto their OCP
addresses, wired as the user MII bus C45 handlers when the chip provides
them (rtl8366rb etc. unaffected).
The hardware manages LPI on its own, so advertise EEE to phylink with
no-op mac_{en,dis}able_tx_lpi callbacks. The LPI timer is a single global
per-speed register, so .set_mac_eee rejects the per-port TX LPI knobs
rather than silently ignoring them.
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
It looks great. Thanks.
Reviewed-by: Luiz Angelo Daros de Luca <luizluca@gmail.com>