[PATCH] Add config phase for dp83td510e phy
From: Julien Blanc <hidden>
Date: 2026-09-02 15:58:09
Subsystem:
ethernet phy library, networking drivers, the rest · Maintainers:
Andrew Lunn, Heiner Kallweit, Andrew Lunn, "David S. Miller", Eric Dumazet, Jakub Kicinski, Paolo Abeni, Linus Torvalds
Add a config phase for the Texas Instruments DP83TD510E ethenet PHY
The config phase currently sets the following properties from the
device tree:
* RMII / RGMII mode (note : RMII master / slave can only be set
by straps and cannot be changed at runtime on this phy)
* RGMII delays. These delays can be enabled on the phy side, only
as a boolean. Delays are enabled if phy-mode is rgmii-id, or
rgmii-[rx|tx]id which enables only the corresponding delay.
Signed-off-by: Julien Blanc <redacted>
---
drivers/net/phy/dp83td510.c | 54 +++++++++++++++++++++++++++++++++++++
1 file changed, 54 insertions(+)
diff --git a/drivers/net/phy/dp83td510.c b/drivers/net/phy/dp83td510.c
index d75dae6071ad..505e3843740f 100644
--- a/drivers/net/phy/dp83td510.c
+++ b/drivers/net/phy/dp83td510.c@@ -30,6 +30,12 @@ #define DP83TD510E_INT1_LINK BIT(13) #define DP83TD510E_INT1_LINK_EN BIT(5) +#define DP83TD510E_RCSR 0x17 +#define DP83TD510E_RMII_MODE_EN BIT(5) +#define DP83TD510E_RGMII_MODE_EN BIT(9) +#define DP83TD510E_TX_CLK_SHIFT BIT(11) +#define DP83TD510E_RX_CLK_SHIFT BIT(12) + #define DP83TD510E_CTRL 0x1f #define DP83TD510E_CTRL_HW_RESET BIT(15) #define DP83TD510E_CTRL_SW_RESET BIT(14)
@@ -646,6 +652,53 @@ static int dp83td510_config_aneg(struct phy_device *phydev) return genphy_c45_check_and_restart_aneg(phydev, changed); } +static int dp83td510_config_init(struct phy_device *phydev) +{ + struct device *dev = &phydev->mdio.dev; + int rgmii_delay = 0; + s32 rx_int_delay; + s32 tx_int_delay; + int ret; + + if (phy_interface_is_rgmii(phydev)) { + rx_int_delay = phy_get_internal_delay(phydev, dev, NULL, 0, + true); + + /* Set DP83TD510E_RX_CLK_SHIFT to enable rx clk internal delay */ + if (rx_int_delay > 0) + rgmii_delay |= DP83TD510E_RX_CLK_SHIFT; + + tx_int_delay = phy_get_internal_delay(phydev, dev, NULL, 0, + false); + + /* Set DP83TD510E_TX_CLK_SHIFT to enable tx clk internal delay */ + if (tx_int_delay > 0) + rgmii_delay |= DP83TD510E_TX_CLK_SHIFT; + + ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_RCSR, + DP83TD510E_RX_CLK_SHIFT | DP83TD510E_TX_CLK_SHIFT, + rgmii_delay); + if (ret) + return ret; + + ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, + DP83TD510E_RCSR, DP83TD510E_RGMII_MODE_EN); + + if (ret) + return ret; + + } else if (phydev->interface == PHY_INTERFACE_MODE_RMII) { + // set RMII_MODE_EN, clear RGMII_MODE_EN (exclusive) + ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_RCSR, + DP83TD510E_RMII_MODE_EN | DP83TD510E_RGMII_MODE_EN, + DP83TD510E_RMII_MODE_EN); + if (ret) + return ret; + } + + return ret; +} + static int dp83td510_get_sqi(struct phy_device *phydev) { int sqi, ret;
@@ -939,6 +992,7 @@ static struct phy_driver dp83td510_driver[] = { .name = "TI DP83TD510E", .flags = PHY_POLL_CABLE_TEST, + .config_init = dp83td510_config_init, .probe = dp83td510_probe, .config_aneg = dp83td510_config_aneg, .read_status = dp83td510_read_status,
--
2.47.3