[PATCH v5 13/25] clk: mediatek: pll: Add ops for PLLs using set/clr regs
From: Louis-Alexis Eyraud <hidden>
Date: 2026-08-01 11:21:58
Also in:
linux-arm-kernel, linux-clk, linux-devicetree, linux-mediatek, lkml
Subsystem:
common clk framework, the rest · Maintainers:
Michael Turquette, Stephen Boyd, Linus Torvalds
MT8189 SoC uses a new combination of status and set/clr registers to
control its PLL enable state and perform BAR reset, that are different
than the current default clock prepare/unprepare operations are using.
Add new set of PLL clock operations to support this logic that relies
on the following registers for prepare/unprepare operations:
- en/en_set/en_clr, rather than en register, for PLL enable
control
- rst_bar/rst_bar_set/rst_bar_clr, rather than default rst_bar
register for BAR reset control
Also, handle rst_bar register setting/clearing with a timeout, to
verify the operation was correctly performed.
Signed-off-by: Louis-Alexis Eyraud <redacted>
---
drivers/clk/mediatek/clk-pll.c | 66 ++++++++++++++++++++++++++++++++++++++++++
drivers/clk/mediatek/clk-pll.h | 5 ++++
2 files changed, 71 insertions(+)
diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c
index 9a197a657dce..3118f68aa9ac 100644
--- a/drivers/clk/mediatek/clk-pll.c
+++ b/drivers/clk/mediatek/clk-pll.c@@ -9,6 +9,7 @@ #include <linux/delay.h> #include <linux/err.h> #include <linux/io.h> +#include <linux/iopoll.h> #include <linux/module.h> #include <linux/of_address.h> #include <linux/platform_device.h>
@@ -32,6 +33,7 @@ #define INTEGER_BITS 7 #define PLL_STABILIZATION_DELAY 20 /* in us */ +#define RST_BAR_TIMEOUT 20 /* in us */ int mtk_pll_is_prepared(struct clk_hw *hw) {
@@ -301,6 +303,60 @@ void mtk_pll_unprepare(struct clk_hw *hw) mtk_pll_power_off(pll); } +int mtk_pll_prepare_setclr(struct clk_hw *hw) +{ + struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); + u32 val = 0; + int ret; + + mtk_pll_power_on(pll); + + writel(BIT(pll->data->pll_en_bit), pll->en_set_addr); + + __mtk_pll_tuner_enable(pll); + + udelay(PLL_STABILIZATION_DELAY); + + if (pll->data->flags & HAVE_RST_BAR) { + writel(pll->data->rst_bar_mask, pll->rst_bar_set_addr); + + ret = readl_poll_timeout(pll->rst_bar_addr, val, + (val & pll->data->rst_bar_mask), 1, + RST_BAR_TIMEOUT); + if (ret) { + mtk_pll_unprepare_setclr(hw); + return ret; + } + } + + return 0; +} +EXPORT_SYMBOL_GPL(mtk_pll_prepare_setclr); + +void mtk_pll_unprepare_setclr(struct clk_hw *hw) +{ + struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); + u32 val = 0; + + if (pll->data->flags & HAVE_RST_BAR) { + writel(pll->data->rst_bar_mask, pll->rst_bar_clr_addr); + + /* ignore return code to continue unpreparing the PLL if + * a error occurs on register read poll. + */ + readl_poll_timeout(pll->rst_bar_addr, val, + !(val & pll->data->rst_bar_mask), 1, + RST_BAR_TIMEOUT); + } + + __mtk_pll_tuner_disable(pll); + + writel(BIT(pll->data->pll_en_bit), pll->en_clr_addr); + + mtk_pll_power_off(pll); +} +EXPORT_SYMBOL_GPL(mtk_pll_unprepare_setclr); + static int mtk_pll_prepare_fenc_setclr(struct clk_hw *hw) { struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
@@ -329,6 +385,16 @@ const struct clk_ops mtk_pll_ops = { .set_rate = mtk_pll_set_rate, }; +const struct clk_ops mtk_pll_setclr_ops = { + .is_prepared = mtk_pll_is_prepared, + .prepare = mtk_pll_prepare_setclr, + .unprepare = mtk_pll_unprepare_setclr, + .recalc_rate = mtk_pll_recalc_rate, + .determine_rate = mtk_pll_determine_rate, + .set_rate = mtk_pll_set_rate, +}; +EXPORT_SYMBOL_GPL(mtk_pll_setclr_ops); + const struct clk_ops mtk_pll_fenc_setclr_ops = { .is_prepared = mtk_pll_is_prepared_fenc_setclr, .prepare = mtk_pll_prepare_fenc_setclr,
diff --git a/drivers/clk/mediatek/clk-pll.h b/drivers/clk/mediatek/clk-pll.h
index 3aaf3a7654b5..296bed073290 100644
--- a/drivers/clk/mediatek/clk-pll.h
+++ b/drivers/clk/mediatek/clk-pll.h@@ -92,6 +92,7 @@ void mtk_clk_unregister_plls(const struct mtk_pll_data *plls, int num_plls, extern const struct clk_ops mtk_pll_ops; extern const struct clk_ops mtk_pll_fenc_setclr_ops; +extern const struct clk_ops mtk_pll_setclr_ops; static inline struct mtk_clk_pll *to_mtk_clk_pll(struct clk_hw *hw) {
@@ -104,6 +105,10 @@ int mtk_pll_prepare(struct clk_hw *hw); void mtk_pll_unprepare(struct clk_hw *hw); +int mtk_pll_prepare_setclr(struct clk_hw *hw); + +void mtk_pll_unprepare_setclr(struct clk_hw *hw); + unsigned long mtk_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate); void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv,
--
2.55.0