[PATCH v5 12/25] clk: mediatek: pll: Add PLL stabilization delay definition
From: Louis-Alexis Eyraud <hidden>
Date: 2026-08-01 11:21:50
Also in:
linux-arm-kernel, linux-clk, linux-devicetree, linux-mediatek, lkml
Subsystem:
common clk framework, the rest · Maintainers:
Michael Turquette, Stephen Boyd, Linus Torvalds
Several functions uses a hardcoded value (20), to represent the needed delay to stabilize a PLL. Add a common define for this value. Signed-off-by: Louis-Alexis Eyraud <redacted> --- drivers/clk/mediatek/clk-pll.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c
index 2aaf2871ecf6..9a197a657dce 100644
--- a/drivers/clk/mediatek/clk-pll.c
+++ b/drivers/clk/mediatek/clk-pll.c@@ -31,6 +31,8 @@ /* default 7 bits integer, can be overridden with pcwibits. */ #define INTEGER_BITS 7 +#define PLL_STABILIZATION_DELAY 20 /* in us */ + int mtk_pll_is_prepared(struct clk_hw *hw) { struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
@@ -131,7 +133,7 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw, /* restore tuner_en */ __mtk_pll_tuner_enable(pll); - udelay(20); + udelay(PLL_STABILIZATION_DELAY); } /*
@@ -264,7 +266,7 @@ int mtk_pll_prepare(struct clk_hw *hw) __mtk_pll_tuner_enable(pll); - udelay(20); + udelay(PLL_STABILIZATION_DELAY); if (pll->data->flags & HAVE_RST_BAR) { r = readl(pll->rst_bar_addr);
@@ -306,7 +308,7 @@ static int mtk_pll_prepare_fenc_setclr(struct clk_hw *hw) writel(BIT(pll->data->pll_en_bit), pll->en_set_addr); /* Wait 20us after enable for the PLL to stabilize */ - udelay(20); + udelay(PLL_STABILIZATION_DELAY); return 0; }
--
2.55.0