[PATCH v3 2/3] arm64: dts: rockchip: describe PCIe RTL8125 Ethernet on NanoPC-T6
From: Ricardo Pardini via B4 Relay <devnull+ricardo.pardini.net@kernel.org>
Date: 2026-06-05 11:49:28
Also in:
b4-sent, linux-arm-kernel, linux-devicetree, linux-rockchip, lkml
Subsystem:
the rest · Maintainer:
Linus Torvalds
From: Ricardo Pardini <redacted> The FriendlyElec NanoPC-T6 carries two on-board Realtek RTL8125 NICs behind pcie2x1l0 and pcie2x1l2. Describe the fixed function nodes and attach ethernet0/ethernet1 aliases, so that U-Boot's fdt_fixup_ethernet() can inject mac-address properties from its ethaddr/eth1addr env. The on-NIC EEPROMs on this board are not pre-programmed with a unique MAC, so this gives a stable MAC across boots that both U-Boot and the kernel agree on. Signed-off-by: Ricardo Pardini <redacted> --- arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi | 30 ++++++++++++++++++++++ 1 file changed, 30 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi
index 84b6b53f016ab..04c4479f08170 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi@@ -20,6 +20,8 @@ / { compatible = "friendlyarm,nanopc-t6", "rockchip,rk3588"; aliases { + ethernet0 = &rtl_eth0; + ethernet1 = &rtl_eth1; mmc0 = &sdhci; mmc1 = &sdmmc; };
@@ -635,6 +637,20 @@ &pcie2x1l0 { pinctrl-names = "default"; pinctrl-0 = <&pcie2_0_rst>; status = "okay"; + + pcie@0,0 { + reg = <0x200000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + device_type = "pci"; + bus-range = <0x20 0x2f>; + + rtl_eth0: ethernet@0,0 { + compatible = "pci10ec,8125"; + reg = <0x210000 0 0 0 0>; + }; + }; }; &pcie2x1l1 {
@@ -651,6 +667,20 @@ &pcie2x1l2 { pinctrl-names = "default"; pinctrl-0 = <&pcie2_2_rst>; status = "okay"; + + pcie@0,0 { + reg = <0x400000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + device_type = "pci"; + bus-range = <0x40 0x4f>; + + rtl_eth1: ethernet@0,0 { + compatible = "pci10ec,8125"; + reg = <0x410000 0 0 0 0>; + }; + }; }; &pcie30phy {
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2.54.0