Re: [PATCH net-next] net: phy: bcm84881: add BCM84891/BCM84892 support

On Tue, Mar 24, 2026 at 06:54:29PM +0000, Daniel Wagner wrote:

Thanks both for the quick review.

On Tue, Mar 24, 2026 at 3:50 PM Russell King (Oracle)
[off-list ref] wrote:

quoted

Is the PHY really using 10GBASE-R or is it using USXGMII. The two are
different.

[...]

quoted

Is there a code in the 0x4011 register which indicates if it uses
USXGMII as opposed to 10GBASE-R ? Please clarify.

It's USXGMII with symbol replication. The MAC receives the negotiated copper
speed, not 10G -- phylink's mac_link_up() is called with the copper speed.
Link works at 100M/1G/2.5G with no rate_matching in the driver, which I think
wouldn't be the case for 10GBASE-R with rate adaptation.

One would expect so.

On 0x4011: it reads the same value (0x3107, mode=3) at 1G and at 2.5G copper,
not tracking copper speed. There's no separate USXGMII encoding I can find --
mode=3 appears to mean "10G SerDes line rate" regardless of protocol, but
admittedly I don't have access to data sheets so this is inference.

Looking at the information I have for this register:
bit 0 should be link bit (0 = link down, 1 = link up)
bits 4:1 indicates the interface and speed over interface:
	3  = 10GBASE-R
	...
	9, 10, 12 and 13 indicate USXGMII at various link speeds.

So, as you're seeing 3 for this field, that makes me somewhat
suspicious whether this register is implemented the same on these
devices.

Can you confirm whether bit 0 changes depending whether the PHY has
link. I don't know whether that's media link or host-side link, so
I suggest checking both.

Thanks.

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