[PATCH net-next 1/5] net: cadence: macb: add EEE register definitions and capability flag
From: Nicolai Buchwitz <hidden>
Date: 2026-02-23 09:05:23
Subsystem:
atmel macb ethernet driver, networking drivers, the rest · Maintainers:
Théo Lebrun, Andrew Lunn, "David S. Miller", Eric Dumazet, Jakub Kicinski, Paolo Abeni, Linus Torvalds
Add register and bitfield definitions for the Cadence GEM MAC's IEEE 802.3az Energy Efficient Ethernet (EEE) support: - LPI statistics counter registers (GEM_RXLPI, GEM_RXLPITIME, GEM_TXLPI, GEM_TXLPITIME) at offsets 0x270-0x27c - TX LPI enable bitfield (GEM_TXLPIEN) in the NCR register (bit 19), which directly asserts/deasserts LPI on the transmit path - MACB_CAPS_EEE capability flag to gate EEE support per platform These registers are present in all Cadence GEM revisions that support EEE (verified on SAMA5D2, SAME70, PIC32CZ, and RP1 variants). No functional change. Signed-off-by: Nicolai Buchwitz <redacted> --- drivers/net/ethernet/cadence/macb.h | 9 +++++++++ 1 file changed, 9 insertions(+)
diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h
index 87414a2ddf6e..f8fdb83bb5f3 100644
--- a/drivers/net/ethernet/cadence/macb.h
+++ b/drivers/net/ethernet/cadence/macb.h@@ -170,6 +170,10 @@ #define GEM_PCSANNPTX 0x021c /* PCS AN Next Page TX */ #define GEM_PCSANNPLP 0x0220 /* PCS AN Next Page LP */ #define GEM_PCSANEXTSTS 0x023c /* PCS AN Extended Status */ +#define GEM_RXLPI 0x0270 /* EEE RX LPI Transitions */ +#define GEM_RXLPITIME 0x0274 /* EEE RX LPI Time */ +#define GEM_TXLPI 0x0278 /* EEE TX LPI Transitions */ +#define GEM_TXLPITIME 0x027c /* EEE TX LPI Time */ #define GEM_DCFG1 0x0280 /* Design Config 1 */ #define GEM_DCFG2 0x0284 /* Design Config 2 */ #define GEM_DCFG3 0x0288 /* Design Config 3 */
@@ -264,6 +268,10 @@ #define MACB_MIIONRGMII_OFFSET 28 /* MII Usage on RGMII Interface */ #define MACB_MIIONRGMII_SIZE 1 +/* GEM specific NCR bitfields. */ +#define GEM_TXLPIEN_OFFSET 19 /* TX LPI Enable */ +#define GEM_TXLPIEN_SIZE 1 + /* Bitfields in NCFGR */ #define MACB_SPD_OFFSET 0 /* Speed */ #define MACB_SPD_SIZE 1
@@ -779,6 +787,7 @@ #define MACB_CAPS_DMA_PTP BIT(22) #define MACB_CAPS_RSC BIT(23) #define MACB_CAPS_NO_LSO BIT(24) +#define MACB_CAPS_EEE BIT(25) /* LSO settings */ #define MACB_LSO_UFO_ENABLE 0x01
--
2.39.5